| Message ID | 20211130212137.25303-3-martin.botka@somainline.org (mailing list archive) |
|---|---|
| State | Changes Requested |
| Headers | show |
| Series | [1/3] dt-bindings: clock: add QCOM SM6125 display clock bindings | expand |
On 2021-11-30 22:21:34, Martin Botka wrote: > Add the dispcc node from the newly added DISPCC > driver for Qualcomm Technology Inc's SM6125 SoC. > > Signed-off-by: Martin Botka <martin.botka@somainline.org> > --- > arch/arm64/boot/dts/qcom/sm6125.dtsi | 12 ++++++++++++ > 1 file changed, 12 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi > index 51286ddbdb10..78f4705e4117 100644 > --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi > @@ -3,6 +3,7 @@ > * Copyright (c) 2021, Martin Botka <martin.botka@somainline.org> > */ > > +#include <dt-bindings/clock/qcom,dispcc-sm6125.h> > #include <dt-bindings/clock/qcom,gcc-sm6125.h> > #include <dt-bindings/clock/qcom,rpmcc.h> > #include <dt-bindings/gpio/gpio.h> > @@ -317,6 +318,17 @@ soc { > ranges = <0x00 0x00 0x00 0xffffffff>; > compatible = "simple-bus"; > > + dispcc: clock-controller@5f00000 { > + #address-cells = <1>; > + #size-cells = <1>; > + compatible = "qcom,dispcc-sm6125"; > + reg = <0x5f00000 0x20000>; > + clocks = <&gcc GCC_DISP_AHB_CLK>; > + clock-names = "cfg_ahb_clk"; It looks like this lacks all the clocks that are supposedly required as per the yaml DT bindings provided in patch 1/3 - should those be added and set to `<0>` where unavailable, otherwise dtbs_check may not pass? > + #clock-cells = <1>; > + #power-domain-cells = <1>; > + }; > + > tcsr_mutex: hwlock@340000 { > compatible = "qcom,tcsr-mutex"; > reg = <0x00340000 0x20000>; > -- > 2.34.0 >
Il 01/12/21 16:51, Marijn Suijten ha scritto: > On 2021-11-30 22:21:34, Martin Botka wrote: >> Add the dispcc node from the newly added DISPCC >> driver for Qualcomm Technology Inc's SM6125 SoC. >> >> Signed-off-by: Martin Botka <martin.botka@somainline.org> >> --- >> arch/arm64/boot/dts/qcom/sm6125.dtsi | 12 ++++++++++++ >> 1 file changed, 12 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi >> index 51286ddbdb10..78f4705e4117 100644 >> --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi >> @@ -3,6 +3,7 @@ >> * Copyright (c) 2021, Martin Botka <martin.botka@somainline.org> >> */ >> >> +#include <dt-bindings/clock/qcom,dispcc-sm6125.h> >> #include <dt-bindings/clock/qcom,gcc-sm6125.h> >> #include <dt-bindings/clock/qcom,rpmcc.h> >> #include <dt-bindings/gpio/gpio.h> >> @@ -317,6 +318,17 @@ soc { >> ranges = <0x00 0x00 0x00 0xffffffff>; >> compatible = "simple-bus"; >> >> + dispcc: clock-controller@5f00000 { >> + #address-cells = <1>; >> + #size-cells = <1>; >> + compatible = "qcom,dispcc-sm6125"; >> + reg = <0x5f00000 0x20000>; >> + clocks = <&gcc GCC_DISP_AHB_CLK>; >> + clock-names = "cfg_ahb_clk"; > > It looks like this lacks all the clocks that are supposedly required as > per the yaml DT bindings provided in patch 1/3 - should those be added > and set to `<0>` where unavailable, otherwise dtbs_check may not pass? > Yes, Marijn. They should. Please Martin, add the missing clocks for v2.
diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi index 51286ddbdb10..78f4705e4117 100644 --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi @@ -3,6 +3,7 @@ * Copyright (c) 2021, Martin Botka <martin.botka@somainline.org> */ +#include <dt-bindings/clock/qcom,dispcc-sm6125.h> #include <dt-bindings/clock/qcom,gcc-sm6125.h> #include <dt-bindings/clock/qcom,rpmcc.h> #include <dt-bindings/gpio/gpio.h> @@ -317,6 +318,17 @@ soc { ranges = <0x00 0x00 0x00 0xffffffff>; compatible = "simple-bus"; + dispcc: clock-controller@5f00000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "qcom,dispcc-sm6125"; + reg = <0x5f00000 0x20000>; + clocks = <&gcc GCC_DISP_AHB_CLK>; + clock-names = "cfg_ahb_clk"; + #clock-cells = <1>; + #power-domain-cells = <1>; + }; + tcsr_mutex: hwlock@340000 { compatible = "qcom,tcsr-mutex"; reg = <0x00340000 0x20000>;
Add the dispcc node from the newly added DISPCC driver for Qualcomm Technology Inc's SM6125 SoC. Signed-off-by: Martin Botka <martin.botka@somainline.org> --- arch/arm64/boot/dts/qcom/sm6125.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+)