| Message ID | cc649faf144fce439b7a341303b6cc73ac285949.1638275062.git.quic_saipraka@quicinc.com (mailing list archive) |
|---|---|
| State | Superseded, archived |
| Headers | show |
| Series | tracing/rwmmio/arm64: Add support to trace register reads/writes | expand |
On Mon, Dec 6, 2021 at 9:28 AM Sai Prakash Ranjan <quic_saipraka@quicinc.com> wrote: > > Remove custom arm64 MMIO accessors read{b,w,l,q} and their relaxed > versions in support to use asm-generic ones. Also define arm64 > barrier macros to override the asm-generic defined barriers. > > Suggested-by: Arnd Bergmann <arnd@arndb.de> > Signed-off-by: Sai Prakash Ranjan <quic_saipraka@quicinc.com> This looks correct, but I would change one detail: > +#define __io_ar(v) __io_par(v) > +#define __io_bw() __iowmb() > +#define __io_br(v) > +#define __io_aw(v) The default __io_par() is defined in terms of __io_ar(), so it would be more logical to remove the custom __io_par() and just define __io_ar() here. I think it would be even better to flip these around and make the low-level definitions __io_ar() and __io_bw(), and then defining the arm64 specific macros based on those: /* arm64-specific, don't use in portable drivers */ #define __iormb(v) __io_ar(v) #define __iowmb() __io_bw() #define __iomb() dma_mb() Arnd
On 12/6/2021 2:20 PM, Arnd Bergmann wrote: > On Mon, Dec 6, 2021 at 9:28 AM Sai Prakash Ranjan > <quic_saipraka@quicinc.com> wrote: >> Remove custom arm64 MMIO accessors read{b,w,l,q} and their relaxed >> versions in support to use asm-generic ones. Also define arm64 >> barrier macros to override the asm-generic defined barriers. >> >> Suggested-by: Arnd Bergmann <arnd@arndb.de> >> Signed-off-by: Sai Prakash Ranjan <quic_saipraka@quicinc.com> > This looks correct, but I would change one detail: > >> +#define __io_ar(v) __io_par(v) >> +#define __io_bw() __iowmb() >> +#define __io_br(v) >> +#define __io_aw(v) > The default __io_par() is defined in terms of __io_ar(), so it would > be more logical > to remove the custom __io_par() and just define __io_ar() here. Makes sense, will do this. > I think it would be even better to flip these around and make the low-level > definitions __io_ar() and __io_bw(), and then defining the arm64 specific > macros based on those: > > /* arm64-specific, don't use in portable drivers */ > #define __iormb(v) __io_ar(v) > #define __iowmb() __io_bw() > #define __iomb() dma_mb() > > So __iormb on arm64 has some dummy control dependency stuff as well based on ("arm64: io: Ensure calls to delay routines are ordered against prior readX()") and then we would need to change __iormb definition to __io_ar which doesn't seem like __iormb definition to be exact right? Thanks, Sai
On Mon, Dec 6, 2021 at 12:12 PM Sai Prakash Ranjan <quic_saipraka@quicinc.com> wrote: > On 12/6/2021 2:20 PM, Arnd Bergmann wrote: > > I think it would be even better to flip these around and make the low-level > > definitions __io_ar() and __io_bw(), and then defining the arm64 specific > > macros based on those: > > > > /* arm64-specific, don't use in portable drivers */ > > #define __iormb(v) __io_ar(v) > > #define __iowmb() __io_bw() > > #define __iomb() dma_mb() > > > > > > So __iormb on arm64 has some dummy control dependency stuff as well based on > ("arm64: io: Ensure calls to delay routines are ordered against prior > readX()") and then we would need to change __iormb definition to __io_ar which > doesn't seem like __iormb definition to be exact right? I'm not sure what you are asking here. As far as I can tell, __io_ar() and __iormb() have the same calling conventions and the same barrier requirements, so they should be interchangeable, we just need to decide which one is the primary definition. Arnd
On 12/6/2021 5:00 PM, Arnd Bergmann wrote: > On Mon, Dec 6, 2021 at 12:12 PM Sai Prakash Ranjan > <quic_saipraka@quicinc.com> wrote: >> On 12/6/2021 2:20 PM, Arnd Bergmann wrote: >>> I think it would be even better to flip these around and make the low-level >>> definitions __io_ar() and __io_bw(), and then defining the arm64 specific >>> macros based on those: >>> >>> /* arm64-specific, don't use in portable drivers */ >>> #define __iormb(v) __io_ar(v) >>> #define __iowmb() __io_bw() >>> #define __iomb() dma_mb() >>> >>> >> So __iormb on arm64 has some dummy control dependency stuff as well based on >> ("arm64: io: Ensure calls to delay routines are ordered against prior >> readX()") and then we would need to change __iormb definition to __io_ar which >> doesn't seem like __iormb definition to be exact right? > I'm not sure what you are asking here. As far as I can tell, __io_ar() > and __iormb() have the same calling conventions and the same barrier > requirements, so they should be interchangeable, we just need to decide > which one is the primary definition. > > Arnd Sorry, what I meant was the literal name of these macros, i.e., __iormb() has more explicit naming as IO read memory barrier and __io_ar() is IO after read? So doesn't it make more sense that __iormb() should be the primary definition which is already the case and ar/bw should be based on them. Thanks, Sai
On Mon, Dec 6, 2021 at 2:52 PM Sai Prakash Ranjan <quic_saipraka@quicinc.com> wrote: > > Sorry, what I meant was the literal name of these macros, i.e., > __iormb() has more explicit naming as > IO read memory barrier and __io_ar() is IO after read? So doesn't it > make more sense that __iormb() > should be the primary definition which is already the case and ar/bw > should be based on them. My reasoning was that we should ideally only have one set, and that __io_ar()/__io_bw() are the ones used in architecture-independent code, so I'd rather use those and deprecate the arm64 specific ones, eventually moving all the arm64 specific code to use those directly where needed. Arnd
Hi Sai,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on arm64/for-next/core]
[also build test WARNING on rostedt-trace/for-next arnd-asm-generic/master arm-perf/for-next/perf v5.16-rc4 next-20211206]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Sai-Prakash-Ranjan/tracing-rwmmio-arm64-Add-support-to-trace-register-reads-writes/20211206-163212
base: https://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux.git for-next/core
config: arm64-randconfig-r014-20211206 (https://download.01.org/0day-ci/archive/20211206/202112062304.8qIQUQyF-lkp@intel.com/config)
compiler: aarch64-linux-gcc (GCC) 11.2.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/0day-ci/linux/commit/0775ecf0f452d6b76b161d009dab52c90270755a
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Sai-Prakash-Ranjan/tracing-rwmmio-arm64-Add-support-to-trace-register-reads-writes/20211206-163212
git checkout 0775ecf0f452d6b76b161d009dab52c90270755a
# save the config file to linux build tree
mkdir build_dir
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.2.0 make.cross O=build_dir ARCH=arm64 SHELL=/bin/bash drivers/gpu/
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All warnings (new ones prefixed by >>):
In file included from drivers/gpu/drm/meson/meson_viu.c:16:
drivers/gpu/drm/meson/meson_viu.c: In function 'meson_viu_init':
>> drivers/gpu/drm/meson/meson_registers.h:1826:55: warning: conversion from 'long unsigned int' to 'u32' {aka 'unsigned int'} changes value from '18446744071814774785' to '2400190465' [-Woverflow]
1826 | #define VIU_OSD_BLEND_REORDER(dest, src) ((src) << (dest * 4))
| ^
drivers/gpu/drm/meson/meson_viu.c:472:32: note: in expansion of macro 'VIU_OSD_BLEND_REORDER'
472 | writel_relaxed(VIU_OSD_BLEND_REORDER(0, 1) |
| ^~~~~~~~~~~~~~~~~~~~~
vim +1826 drivers/gpu/drm/meson/meson_registers.h
b93a66faeea9ddf Neil Armstrong 2019-03-25 1824
b93a66faeea9ddf Neil Armstrong 2019-03-25 1825 #define VIU_OSD_BLEND_CTRL 0x39b0
147ae1cbaa18429 Julien Masson 2019-06-24 @1826 #define VIU_OSD_BLEND_REORDER(dest, src) ((src) << (dest * 4))
147ae1cbaa18429 Julien Masson 2019-06-24 1827 #define VIU_OSD_BLEND_DIN_EN(bits) ((bits & 0xf) << 20)
147ae1cbaa18429 Julien Masson 2019-06-24 1828 #define VIU_OSD_BLEND1_DIN3_BYPASS_TO_DOUT1 BIT(24)
147ae1cbaa18429 Julien Masson 2019-06-24 1829 #define VIU_OSD_BLEND1_DOUT_BYPASS_TO_BLEND2 BIT(25)
147ae1cbaa18429 Julien Masson 2019-06-24 1830 #define VIU_OSD_BLEND_DIN0_BYPASS_TO_DOUT0 BIT(26)
147ae1cbaa18429 Julien Masson 2019-06-24 1831 #define VIU_OSD_BLEND_BLEN2_PREMULT_EN(input) ((input & 0x3) << 27)
147ae1cbaa18429 Julien Masson 2019-06-24 1832 #define VIU_OSD_BLEND_HOLD_LINES(lines) ((lines & 0x7) << 29)
b93a66faeea9ddf Neil Armstrong 2019-03-25 1833 #define VIU_OSD_BLEND_CTRL1 0x39c0
b93a66faeea9ddf Neil Armstrong 2019-03-25 1834 #define VIU_OSD_BLEND_DIN0_SCOPE_H 0x39b1
b93a66faeea9ddf Neil Armstrong 2019-03-25 1835 #define VIU_OSD_BLEND_DIN0_SCOPE_V 0x39b2
b93a66faeea9ddf Neil Armstrong 2019-03-25 1836 #define VIU_OSD_BLEND_DIN1_SCOPE_H 0x39b3
b93a66faeea9ddf Neil Armstrong 2019-03-25 1837 #define VIU_OSD_BLEND_DIN1_SCOPE_V 0x39b4
b93a66faeea9ddf Neil Armstrong 2019-03-25 1838 #define VIU_OSD_BLEND_DIN2_SCOPE_H 0x39b5
b93a66faeea9ddf Neil Armstrong 2019-03-25 1839 #define VIU_OSD_BLEND_DIN2_SCOPE_V 0x39b6
b93a66faeea9ddf Neil Armstrong 2019-03-25 1840 #define VIU_OSD_BLEND_DIN3_SCOPE_H 0x39b7
b93a66faeea9ddf Neil Armstrong 2019-03-25 1841 #define VIU_OSD_BLEND_DIN3_SCOPE_V 0x39b8
b93a66faeea9ddf Neil Armstrong 2019-03-25 1842 #define VIU_OSD_BLEND_DUMMY_DATA0 0x39b9
b93a66faeea9ddf Neil Armstrong 2019-03-25 1843 #define VIU_OSD_BLEND_DUMMY_ALPHA 0x39ba
b93a66faeea9ddf Neil Armstrong 2019-03-25 1844 #define VIU_OSD_BLEND_BLEND0_SIZE 0x39bb
b93a66faeea9ddf Neil Armstrong 2019-03-25 1845 #define VIU_OSD_BLEND_BLEND1_SIZE 0x39bc
b93a66faeea9ddf Neil Armstrong 2019-03-25 1846 #define VIU_OSD_BLEND_RO_CURRENT_XY 0x39bf
b93a66faeea9ddf Neil Armstrong 2019-03-25 1847
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
On 12/6/2021 8:45 PM, Arnd Bergmann wrote: > On Mon, Dec 6, 2021 at 2:52 PM Sai Prakash Ranjan > <quic_saipraka@quicinc.com> wrote: >> Sorry, what I meant was the literal name of these macros, i.e., >> __iormb() has more explicit naming as >> IO read memory barrier and __io_ar() is IO after read? So doesn't it >> make more sense that __iormb() >> should be the primary definition which is already the case and ar/bw >> should be based on them. > My reasoning was that we should ideally only have one set, and that > __io_ar()/__io_bw() are the ones used in architecture-independent code, > so I'd rather use those and deprecate the arm64 specific ones, eventually > moving all the arm64 specific code to use those directly where needed. > > Arnd Ah ok, good enough. I will do this in the next version. Thanks, Sai
Hi Sai,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on arm64/for-next/core]
[also build test WARNING on rostedt-trace/for-next arnd-asm-generic/master arm-perf/for-next/perf v5.16-rc4 next-20211207]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Sai-Prakash-Ranjan/tracing-rwmmio-arm64-Add-support-to-trace-register-reads-writes/20211206-163212
base: https://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux.git for-next/core
config: arm64-randconfig-r022-20211207 (https://download.01.org/0day-ci/archive/20211207/202112072058.SZ9tPvIm-lkp@intel.com/config)
compiler: clang version 14.0.0 (https://github.com/llvm/llvm-project 097a1cb1d5ebb3a0ec4bcaed8ba3ff6a8e33c00a)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# install arm64 cross compiling tool for clang build
# apt-get install binutils-aarch64-linux-gnu
# https://github.com/0day-ci/linux/commit/0775ecf0f452d6b76b161d009dab52c90270755a
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Sai-Prakash-Ranjan/tracing-rwmmio-arm64-Add-support-to-trace-register-reads-writes/20211206-163212
git checkout 0775ecf0f452d6b76b161d009dab52c90270755a
# save the config file to linux build tree
mkdir build_dir
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=arm64 SHELL=/bin/bash drivers/gpu/drm/meson/
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All warnings (new ones prefixed by >>):
>> drivers/gpu/drm/meson/meson_viu.c:480:45: warning: implicit conversion from 'unsigned long' to 'u32' (aka 'unsigned int') changes value from 18446744071814774785 to 2400190465 [-Wconstant-conversion]
VIU_OSD_BLEND_BLEN2_PREMULT_EN(1) |
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^
1 warning generated.
vim +480 drivers/gpu/drm/meson/meson_viu.c
1b85270ff156d56 Neil Armstrong 2019-10-21 413
bbbe775ec5b5dac Neil Armstrong 2016-11-10 414 void meson_viu_init(struct meson_drm *priv)
bbbe775ec5b5dac Neil Armstrong 2016-11-10 415 {
bbbe775ec5b5dac Neil Armstrong 2016-11-10 416 uint32_t reg;
bbbe775ec5b5dac Neil Armstrong 2016-11-10 417
bbbe775ec5b5dac Neil Armstrong 2016-11-10 418 /* Disable OSDs */
147ae1cbaa18429 Julien Masson 2019-06-24 419 writel_bits_relaxed(VIU_OSD1_OSD_BLK_ENABLE | VIU_OSD1_OSD_ENABLE, 0,
bbbe775ec5b5dac Neil Armstrong 2016-11-10 420 priv->io_base + _REG(VIU_OSD1_CTRL_STAT));
147ae1cbaa18429 Julien Masson 2019-06-24 421 writel_bits_relaxed(VIU_OSD1_OSD_BLK_ENABLE | VIU_OSD1_OSD_ENABLE, 0,
bbbe775ec5b5dac Neil Armstrong 2016-11-10 422 priv->io_base + _REG(VIU_OSD2_CTRL_STAT));
bbbe775ec5b5dac Neil Armstrong 2016-11-10 423
bbbe775ec5b5dac Neil Armstrong 2016-11-10 424 /* On GXL/GXM, Use the 10bit HDR conversion matrix */
528a25d040bc212 Julien Masson 2019-08-22 425 if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) ||
528a25d040bc212 Julien Masson 2019-08-22 426 meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL))
bbbe775ec5b5dac Neil Armstrong 2016-11-10 427 meson_viu_load_matrix(priv);
bf33677a3c394bb Christian Hewitt 2021-08-06 428 else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) {
728883948b0d3c0 Neil Armstrong 2019-03-25 429 meson_viu_set_g12a_osd1_matrix(priv, RGB709_to_YUV709l_coeff,
728883948b0d3c0 Neil Armstrong 2019-03-25 430 true);
bf33677a3c394bb Christian Hewitt 2021-08-06 431 /* fix green/pink color distortion from vendor u-boot */
bf33677a3c394bb Christian Hewitt 2021-08-06 432 writel_bits_relaxed(OSD1_HDR2_CTRL_REG_ONLY_MAT |
bf33677a3c394bb Christian Hewitt 2021-08-06 433 OSD1_HDR2_CTRL_VDIN0_HDR2_TOP_EN, 0,
bf33677a3c394bb Christian Hewitt 2021-08-06 434 priv->io_base + _REG(OSD1_HDR2_CTRL));
bf33677a3c394bb Christian Hewitt 2021-08-06 435 }
bbbe775ec5b5dac Neil Armstrong 2016-11-10 436
bbbe775ec5b5dac Neil Armstrong 2016-11-10 437 /* Initialize OSD1 fifo control register */
147ae1cbaa18429 Julien Masson 2019-06-24 438 reg = VIU_OSD_DDR_PRIORITY_URGENT |
24e0d4058eff7cd Neil Armstrong 2019-10-21 439 VIU_OSD_HOLD_FIFO_LINES(31) |
147ae1cbaa18429 Julien Masson 2019-06-24 440 VIU_OSD_FIFO_DEPTH_VAL(32) | /* fifo_depth_val: 32*8=256 */
147ae1cbaa18429 Julien Masson 2019-06-24 441 VIU_OSD_WORDS_PER_BURST(4) | /* 4 words in 1 burst */
147ae1cbaa18429 Julien Masson 2019-06-24 442 VIU_OSD_FIFO_LIMITS(2); /* fifo_lim: 2*16=32 */
147ae1cbaa18429 Julien Masson 2019-06-24 443
528a25d040bc212 Julien Masson 2019-08-22 444 if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A))
17f64701ea6f541 Martin Blumenstingl 2020-06-20 445 reg |= VIU_OSD_BURST_LENGTH_32;
728883948b0d3c0 Neil Armstrong 2019-03-25 446 else
17f64701ea6f541 Martin Blumenstingl 2020-06-20 447 reg |= VIU_OSD_BURST_LENGTH_64;
147ae1cbaa18429 Julien Masson 2019-06-24 448
bbbe775ec5b5dac Neil Armstrong 2016-11-10 449 writel_relaxed(reg, priv->io_base + _REG(VIU_OSD1_FIFO_CTRL_STAT));
bbbe775ec5b5dac Neil Armstrong 2016-11-10 450 writel_relaxed(reg, priv->io_base + _REG(VIU_OSD2_FIFO_CTRL_STAT));
bbbe775ec5b5dac Neil Armstrong 2016-11-10 451
bbbe775ec5b5dac Neil Armstrong 2016-11-10 452 /* Set OSD alpha replace value */
bbbe775ec5b5dac Neil Armstrong 2016-11-10 453 writel_bits_relaxed(0xff << OSD_REPLACE_SHIFT,
bbbe775ec5b5dac Neil Armstrong 2016-11-10 454 0xff << OSD_REPLACE_SHIFT,
bbbe775ec5b5dac Neil Armstrong 2016-11-10 455 priv->io_base + _REG(VIU_OSD1_CTRL_STAT2));
bbbe775ec5b5dac Neil Armstrong 2016-11-10 456 writel_bits_relaxed(0xff << OSD_REPLACE_SHIFT,
bbbe775ec5b5dac Neil Armstrong 2016-11-10 457 0xff << OSD_REPLACE_SHIFT,
bbbe775ec5b5dac Neil Armstrong 2016-11-10 458 priv->io_base + _REG(VIU_OSD2_CTRL_STAT2));
bbbe775ec5b5dac Neil Armstrong 2016-11-10 459
f9a2348196d1ab9 Neil Armstrong 2018-11-06 460 /* Disable VD1 AFBC */
147ae1cbaa18429 Julien Masson 2019-06-24 461 /* di_mif0_en=0 mif0_to_vpp_en=0 di_mad_en=0 and afbc vd1 set=0*/
147ae1cbaa18429 Julien Masson 2019-06-24 462 writel_bits_relaxed(VIU_CTRL0_VD1_AFBC_MASK, 0,
f9a2348196d1ab9 Neil Armstrong 2018-11-06 463 priv->io_base + _REG(VIU_MISC_CTRL0));
f9a2348196d1ab9 Neil Armstrong 2018-11-06 464 writel_relaxed(0, priv->io_base + _REG(AFBC_ENABLE));
f9a2348196d1ab9 Neil Armstrong 2018-11-06 465
f9a2348196d1ab9 Neil Armstrong 2018-11-06 466 writel_relaxed(0x00FF00C0,
f9a2348196d1ab9 Neil Armstrong 2018-11-06 467 priv->io_base + _REG(VD1_IF0_LUMA_FIFO_SIZE));
f9a2348196d1ab9 Neil Armstrong 2018-11-06 468 writel_relaxed(0x00FF00C0,
f9a2348196d1ab9 Neil Armstrong 2018-11-06 469 priv->io_base + _REG(VD2_IF0_LUMA_FIFO_SIZE));
f9a2348196d1ab9 Neil Armstrong 2018-11-06 470
528a25d040bc212 Julien Masson 2019-08-22 471 if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) {
147ae1cbaa18429 Julien Masson 2019-06-24 472 writel_relaxed(VIU_OSD_BLEND_REORDER(0, 1) |
147ae1cbaa18429 Julien Masson 2019-06-24 473 VIU_OSD_BLEND_REORDER(1, 0) |
147ae1cbaa18429 Julien Masson 2019-06-24 474 VIU_OSD_BLEND_REORDER(2, 0) |
147ae1cbaa18429 Julien Masson 2019-06-24 475 VIU_OSD_BLEND_REORDER(3, 0) |
147ae1cbaa18429 Julien Masson 2019-06-24 476 VIU_OSD_BLEND_DIN_EN(1) |
147ae1cbaa18429 Julien Masson 2019-06-24 477 VIU_OSD_BLEND1_DIN3_BYPASS_TO_DOUT1 |
147ae1cbaa18429 Julien Masson 2019-06-24 478 VIU_OSD_BLEND1_DOUT_BYPASS_TO_BLEND2 |
147ae1cbaa18429 Julien Masson 2019-06-24 479 VIU_OSD_BLEND_DIN0_BYPASS_TO_DOUT0 |
147ae1cbaa18429 Julien Masson 2019-06-24 @480 VIU_OSD_BLEND_BLEN2_PREMULT_EN(1) |
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
diff --git a/arch/arm64/include/asm/io.h b/arch/arm64/include/asm/io.h index 7fd836bea7eb..33de60fdf6f1 100644 --- a/arch/arm64/include/asm/io.h +++ b/arch/arm64/include/asm/io.h @@ -112,35 +112,10 @@ static inline u64 __raw_readq(const volatile void __iomem *addr) #define __iowmb() dma_wmb() #define __iomb() dma_mb() -/* - * Relaxed I/O memory access primitives. These follow the Device memory - * ordering rules but do not guarantee any ordering relative to Normal memory - * accesses. - */ -#define readb_relaxed(c) ({ u8 __r = __raw_readb(c); __r; }) -#define readw_relaxed(c) ({ u16 __r = le16_to_cpu((__force __le16)__raw_readw(c)); __r; }) -#define readl_relaxed(c) ({ u32 __r = le32_to_cpu((__force __le32)__raw_readl(c)); __r; }) -#define readq_relaxed(c) ({ u64 __r = le64_to_cpu((__force __le64)__raw_readq(c)); __r; }) - -#define writeb_relaxed(v,c) ((void)__raw_writeb((v),(c))) -#define writew_relaxed(v,c) ((void)__raw_writew((__force u16)cpu_to_le16(v),(c))) -#define writel_relaxed(v,c) ((void)__raw_writel((__force u32)cpu_to_le32(v),(c))) -#define writeq_relaxed(v,c) ((void)__raw_writeq((__force u64)cpu_to_le64(v),(c))) - -/* - * I/O memory access primitives. Reads are ordered relative to any - * following Normal memory access. Writes are ordered relative to any prior - * Normal memory access. - */ -#define readb(c) ({ u8 __v = readb_relaxed(c); __iormb(__v); __v; }) -#define readw(c) ({ u16 __v = readw_relaxed(c); __iormb(__v); __v; }) -#define readl(c) ({ u32 __v = readl_relaxed(c); __iormb(__v); __v; }) -#define readq(c) ({ u64 __v = readq_relaxed(c); __iormb(__v); __v; }) - -#define writeb(v,c) ({ __iowmb(); writeb_relaxed((v),(c)); }) -#define writew(v,c) ({ __iowmb(); writew_relaxed((v),(c)); }) -#define writel(v,c) ({ __iowmb(); writel_relaxed((v),(c)); }) -#define writeq(v,c) ({ __iowmb(); writeq_relaxed((v),(c)); }) +#define __io_ar(v) __io_par(v) +#define __io_bw() __iowmb() +#define __io_br(v) +#define __io_aw(v) /* * I/O port access primitives.
Remove custom arm64 MMIO accessors read{b,w,l,q} and their relaxed versions in support to use asm-generic ones. Also define arm64 barrier macros to override the asm-generic defined barriers. Suggested-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Sai Prakash Ranjan <quic_saipraka@quicinc.com> --- arch/arm64/include/asm/io.h | 33 ++++----------------------------- 1 file changed, 4 insertions(+), 29 deletions(-)