| Message ID | 20211210013129.811-5-biao.huang@mediatek.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | MediaTek Ethernet Patches on MT8195 | expand |
On Fri, 10 Dec 2021 09:31:27 +0800, Biao Huang wrote: > Convert mediatek-dwmac to DT schema, and delete old mediatek-dwmac.txt. > And there are some changes in .yaml than .txt, others almost keep the same: > 1. compatible "const: snps,dwmac-4.20". > 2. delete "snps,reset-active-low;" in example, since driver remove this > property long ago. > 3. add "snps,reset-delay-us = <0 10000 10000>" in example. > 4. the example is for rgmii interface, keep related properties only. > > Signed-off-by: Biao Huang <biao.huang@mediatek.com> > --- > .../bindings/net/mediatek-dwmac.txt | 91 ---------- > .../bindings/net/mediatek-dwmac.yaml | 156 ++++++++++++++++++ > 2 files changed, 156 insertions(+), 91 deletions(-) > delete mode 100644 Documentation/devicetree/bindings/net/mediatek-dwmac.txt > create mode 100644 Documentation/devicetree/bindings/net/mediatek-dwmac.yaml > Running 'make dtbs_check' with the schema in this patch gives the following warnings. Consider if they are expected or the schema is incorrect. These may not be new warnings. Note that it is not yet a requirement to have 0 warnings for dtbs_check. This will change in the future. Full log is available here: https://patchwork.ozlabs.org/patch/1566169 ethernet@1101c000: clock-names: ['axi', 'apb', 'mac_main', 'ptp_ref'] is too short arch/arm64/boot/dts/mediatek/mt2712-evb.dt.yaml ethernet@1101c000: clocks: [[27, 34], [27, 37], [6, 154], [6, 155]] is too short arch/arm64/boot/dts/mediatek/mt2712-evb.dt.yaml ethernet@1101c000: compatible: ['mediatek,mt2712-gmac'] does not contain items matching the given schema arch/arm64/boot/dts/mediatek/mt2712-evb.dt.yaml ethernet@1101c000: compatible: 'oneOf' conditional failed, one must be fixed: arch/arm64/boot/dts/mediatek/mt2712-evb.dt.yaml ethernet@1101c000: Unevaluated properties are not allowed ('compatible', 'reg', 'interrupts', 'interrupt-names', 'mac-address', 'clock-names', 'clocks', 'power-domains', 'snps,axi-config', 'snps,mtl-rx-config', 'snps,mtl-tx-config', 'snps,txpbl', 'snps,rxpbl', 'clk_csr', 'phy-mode', 'phy-handle', 'snps,reset-gpio', 'mdio' were unexpected) arch/arm64/boot/dts/mediatek/mt2712-evb.dt.yaml
On Fri, Dec 10, 2021 at 09:31:27AM +0800, Biao Huang wrote: > Convert mediatek-dwmac to DT schema, and delete old mediatek-dwmac.txt. > And there are some changes in .yaml than .txt, others almost keep the same: > 1. compatible "const: snps,dwmac-4.20". > 2. delete "snps,reset-active-low;" in example, since driver remove this > property long ago. > 3. add "snps,reset-delay-us = <0 10000 10000>" in example. > 4. the example is for rgmii interface, keep related properties only. > > Signed-off-by: Biao Huang <biao.huang@mediatek.com> > --- > .../bindings/net/mediatek-dwmac.txt | 91 ---------- > .../bindings/net/mediatek-dwmac.yaml | 156 ++++++++++++++++++ > 2 files changed, 156 insertions(+), 91 deletions(-) > delete mode 100644 Documentation/devicetree/bindings/net/mediatek-dwmac.txt > create mode 100644 Documentation/devicetree/bindings/net/mediatek-dwmac.yaml > > diff --git a/Documentation/devicetree/bindings/net/mediatek-dwmac.txt b/Documentation/devicetree/bindings/net/mediatek-dwmac.txt > deleted file mode 100644 > index afbcaebf062e..000000000000 > --- a/Documentation/devicetree/bindings/net/mediatek-dwmac.txt > +++ /dev/null > @@ -1,91 +0,0 @@ > -MediaTek DWMAC glue layer controller > - > -This file documents platform glue layer for stmmac. > -Please see stmmac.txt for the other unchanged properties. > - > -The device node has following properties. > - > -Required properties: > -- compatible: Should be "mediatek,mt2712-gmac" for MT2712 SoC > -- reg: Address and length of the register set for the device > -- interrupts: Should contain the MAC interrupts > -- interrupt-names: Should contain a list of interrupt names corresponding to > - the interrupts in the interrupts property, if available. > - Should be "macirq" for the main MAC IRQ > -- clocks: Must contain a phandle for each entry in clock-names. > -- clock-names: The name of the clock listed in the clocks property. These are > - "axi", "apb", "mac_main", "ptp_ref", "rmii_internal" for MT2712 SoC. > -- mac-address: See ethernet.txt in the same directory > -- phy-mode: See ethernet.txt in the same directory > -- mediatek,pericfg: A phandle to the syscon node that control ethernet > - interface and timing delay. > - > -Optional properties: > -- mediatek,tx-delay-ps: TX clock delay macro value. Default is 0. > - It should be defined for RGMII/MII interface. > - It should be defined for RMII interface when the reference clock is from MT2712 SoC. > -- mediatek,rx-delay-ps: RX clock delay macro value. Default is 0. > - It should be defined for RGMII/MII interface. > - It should be defined for RMII interface. > -Both delay properties need to be a multiple of 170 for RGMII interface, > -or will round down. Range 0~31*170. > -Both delay properties need to be a multiple of 550 for MII/RMII interface, > -or will round down. Range 0~31*550. > - > -- mediatek,rmii-rxc: boolean property, if present indicates that the RMII > - reference clock, which is from external PHYs, is connected to RXC pin > - on MT2712 SoC. > - Otherwise, is connected to TXC pin. > -- mediatek,rmii-clk-from-mac: boolean property, if present indicates that > - MT2712 SoC provides the RMII reference clock, which outputs to TXC pin only. > -- mediatek,txc-inverse: boolean property, if present indicates that > - 1. tx clock will be inversed in MII/RGMII case, > - 2. tx clock inside MAC will be inversed relative to reference clock > - which is from external PHYs in RMII case, and it rarely happen. > - 3. the reference clock, which outputs to TXC pin will be inversed in RMII case > - when the reference clock is from MT2712 SoC. > -- mediatek,rxc-inverse: boolean property, if present indicates that > - 1. rx clock will be inversed in MII/RGMII case. > - 2. reference clock will be inversed when arrived at MAC in RMII case, when > - the reference clock is from external PHYs. > - 3. the inside clock, which be sent to MAC, will be inversed in RMII case when > - the reference clock is from MT2712 SoC. > -- assigned-clocks: mac_main and ptp_ref clocks > -- assigned-clock-parents: parent clocks of the assigned clocks > - > -Example: > - eth: ethernet@1101c000 { > - compatible = "mediatek,mt2712-gmac"; > - reg = <0 0x1101c000 0 0x1300>; > - interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_LOW>; > - interrupt-names = "macirq"; > - phy-mode ="rgmii-rxid"; > - mac-address = [00 55 7b b5 7d f7]; > - clock-names = "axi", > - "apb", > - "mac_main", > - "ptp_ref", > - "rmii_internal"; > - clocks = <&pericfg CLK_PERI_GMAC>, > - <&pericfg CLK_PERI_GMAC_PCLK>, > - <&topckgen CLK_TOP_ETHER_125M_SEL>, > - <&topckgen CLK_TOP_ETHER_50M_SEL>, > - <&topckgen CLK_TOP_ETHER_50M_RMII_SEL>; > - assigned-clocks = <&topckgen CLK_TOP_ETHER_125M_SEL>, > - <&topckgen CLK_TOP_ETHER_50M_SEL>, > - <&topckgen CLK_TOP_ETHER_50M_RMII_SEL>; > - assigned-clock-parents = <&topckgen CLK_TOP_ETHERPLL_125M>, > - <&topckgen CLK_TOP_APLL1_D3>, > - <&topckgen CLK_TOP_ETHERPLL_50M>; > - power-domains = <&scpsys MT2712_POWER_DOMAIN_AUDIO>; > - mediatek,pericfg = <&pericfg>; > - mediatek,tx-delay-ps = <1530>; > - mediatek,rx-delay-ps = <1530>; > - mediatek,rmii-rxc; > - mediatek,txc-inverse; > - mediatek,rxc-inverse; > - snps,txpbl = <1>; > - snps,rxpbl = <1>; > - snps,reset-gpio = <&pio 87 GPIO_ACTIVE_LOW>; > - snps,reset-active-low; > - }; > diff --git a/Documentation/devicetree/bindings/net/mediatek-dwmac.yaml b/Documentation/devicetree/bindings/net/mediatek-dwmac.yaml > new file mode 100644 > index 000000000000..9207266a6e69 > --- /dev/null > +++ b/Documentation/devicetree/bindings/net/mediatek-dwmac.yaml > @@ -0,0 +1,156 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/net/mediatek-dwmac.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: MediaTek DWMAC glue layer controller > + > +maintainers: > + - Biao Huang <biao.huang@mediatek.com> > + > +description: > + This file documents platform glue layer for stmmac. > + > +# We need a select here so we don't match all nodes with 'snps,dwmac' > +select: > + properties: > + compatible: > + contains: > + enum: > + - mediatek,mt2712-gmac > + required: > + - compatible > + > +allOf: > + - $ref: "snps,dwmac.yaml#" > + > +properties: > + compatible: > + oneOf: > + - items: Don't need oneOf for 1 entry. > + - enum: > + - mediatek,mt2712-gmac > + - const: snps,dwmac-4.20a > + > + clocks: > + items: > + - description: AXI clock > + - description: APB clock > + - description: MAC Main clock > + - description: PTP clock > + - description: RMII reference clock provided by MAC Seems you need 'minItems: 4' or are the DT files wrong? > + > + clock-names: > + items: > + - const: axi > + - const: apb > + - const: mac_main > + - const: ptp_ref > + - const: rmii_internal > + > + mediatek,pericfg: > + $ref: /schemas/types.yaml#/definitions/phandle > + description: > + The phandle to the syscon node that control ethernet > + interface and timing delay. > + > + mediatek,tx-delay-ps: > + description: > + The internal TX clock delay (provided by this driver) in nanoseconds. > + For MT2712 RGMII interface, Allowed value need to be a multiple of 170, > + or will round down. Range 0~31*170. > + For MT2712 RMII/MII interface, Allowed value need to be a multiple of 550, > + or will round down. Range 0~31*550. > + > + mediatek,rx-delay-ps: > + description: > + The internal RX clock delay (provided by this driver) in nanoseconds. > + For MT2712 RGMII interface, Allowed value need to be a multiple of 170, > + or will round down. Range 0~31*170. > + For MT2712 RMII/MII interface, Allowed value need to be a multiple of 550, > + or will round down. Range 0~31*550. > + > + mediatek,rmii-rxc: > + type: boolean > + description: > + If present, indicates that the RMII reference clock, which is from external > + PHYs, is connected to RXC pin. Otherwise, is connected to TXC pin. > + > + mediatek,rmii-clk-from-mac: > + type: boolean > + description: > + If present, indicates that MAC provides the RMII reference clock, which > + outputs to TXC pin only. > + > + mediatek,txc-inverse: > + type: boolean > + description: > + If present, indicates that > + 1. tx clock will be inversed in MII/RGMII case, > + 2. tx clock inside MAC will be inversed relative to reference clock > + which is from external PHYs in RMII case, and it rarely happen. > + 3. the reference clock, which outputs to TXC pin will be inversed in RMII case > + when the reference clock is from MAC. > + > + mediatek,rxc-inverse: > + type: boolean > + description: > + If present, indicates that > + 1. rx clock will be inversed in MII/RGMII case. > + 2. reference clock will be inversed when arrived at MAC in RMII case, when > + the reference clock is from external PHYs. > + 3. the inside clock, which be sent to MAC, will be inversed in RMII case when > + the reference clock is from MAC. > + > +required: > + - compatible > + - reg > + - interrupts > + - interrupt-names > + - clocks > + - clock-names > + - phy-mode > + - mediatek,pericfg > + > +unevaluatedProperties: false > + > +examples: > + - | > + #include <dt-bindings/clock/mt2712-clk.h> > + #include <dt-bindings/gpio/gpio.h> > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + #include <dt-bindings/interrupt-controller/irq.h> > + #include <dt-bindings/power/mt2712-power.h> > + > + eth: ethernet@1101c000 { > + compatible = "mediatek,mt2712-gmac", "snps,dwmac-4.20a"; > + reg = <0x1101c000 0x1300>; > + interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_LOW>; > + interrupt-names = "macirq"; > + phy-mode ="rgmii-rxid"; > + mac-address = [00 55 7b b5 7d f7]; > + clock-names = "axi", > + "apb", > + "mac_main", > + "ptp_ref", > + "rmii_internal"; > + clocks = <&pericfg CLK_PERI_GMAC>, > + <&pericfg CLK_PERI_GMAC_PCLK>, > + <&topckgen CLK_TOP_ETHER_125M_SEL>, > + <&topckgen CLK_TOP_ETHER_50M_SEL>, > + <&topckgen CLK_TOP_ETHER_50M_RMII_SEL>; > + assigned-clocks = <&topckgen CLK_TOP_ETHER_125M_SEL>, > + <&topckgen CLK_TOP_ETHER_50M_SEL>, > + <&topckgen CLK_TOP_ETHER_50M_RMII_SEL>; > + assigned-clock-parents = <&topckgen CLK_TOP_ETHERPLL_125M>, > + <&topckgen CLK_TOP_APLL1_D3>, > + <&topckgen CLK_TOP_ETHERPLL_50M>; > + power-domains = <&scpsys MT2712_POWER_DOMAIN_AUDIO>; > + mediatek,pericfg = <&pericfg>; > + mediatek,tx-delay-ps = <1530>; > + snps,txpbl = <1>; > + snps,rxpbl = <1>; > + snps,reset-gpio = <&pio 87 GPIO_ACTIVE_LOW>; > + snps,reset-delays-us = <0 10000 10000>; > + }; > -- > 2.25.1 > >
Dear Rob, Thanks for your comments~ On Fri, 2021-12-10 at 12:49 -0600, Rob Herring wrote: > On Fri, Dec 10, 2021 at 09:31:27AM +0800, Biao Huang wrote: > > Convert mediatek-dwmac to DT schema, and delete old mediatek- > > dwmac.txt. > > And there are some changes in .yaml than .txt, others almost keep > > the same: > > 1. compatible "const: snps,dwmac-4.20". > > 2. delete "snps,reset-active-low;" in example, since driver > > remove this > > property long ago. > > 3. add "snps,reset-delay-us = <0 10000 10000>" in example. > > 4. the example is for rgmii interface, keep related properties > > only. > > > > Signed-off-by: Biao Huang <biao.huang@mediatek.com> > > --- > > .../bindings/net/mediatek-dwmac.txt | 91 ---------- > > .../bindings/net/mediatek-dwmac.yaml | 156 > > ++++++++++++++++++ > > 2 files changed, 156 insertions(+), 91 deletions(-) > > delete mode 100644 Documentation/devicetree/bindings/net/mediatek- > > dwmac.txt > > create mode 100644 Documentation/devicetree/bindings/net/mediatek- > > dwmac.yaml > > > > diff --git a/Documentation/devicetree/bindings/net/mediatek- > > dwmac.txt b/Documentation/devicetree/bindings/net/mediatek- > > dwmac.txt > > deleted file mode 100644 > > index afbcaebf062e..000000000000 > > --- a/Documentation/devicetree/bindings/net/mediatek-dwmac.txt > > +++ /dev/null > > @@ -1,91 +0,0 @@ > > -MediaTek DWMAC glue layer controller > > - > > -This file documents platform glue layer for stmmac. > > -Please see stmmac.txt for the other unchanged properties. > > - > > -The device node has following properties. > > - > > -Required properties: > > -- compatible: Should be "mediatek,mt2712-gmac" for MT2712 SoC > > -- reg: Address and length of the register set for the device > > -- interrupts: Should contain the MAC interrupts > > -- interrupt-names: Should contain a list of interrupt names > > corresponding to > > - the interrupts in the interrupts property, if available. > > - Should be "macirq" for the main MAC IRQ > > -- clocks: Must contain a phandle for each entry in clock-names. > > -- clock-names: The name of the clock listed in the clocks > > property. These are > > - "axi", "apb", "mac_main", "ptp_ref", "rmii_internal" for MT2712 > > SoC. > > -- mac-address: See ethernet.txt in the same directory > > -- phy-mode: See ethernet.txt in the same directory > > -- mediatek,pericfg: A phandle to the syscon node that control > > ethernet > > - interface and timing delay. > > - > > -Optional properties: > > -- mediatek,tx-delay-ps: TX clock delay macro value. Default is 0. > > - It should be defined for RGMII/MII interface. > > - It should be defined for RMII interface when the reference > > clock is from MT2712 SoC. > > -- mediatek,rx-delay-ps: RX clock delay macro value. Default is 0. > > - It should be defined for RGMII/MII interface. > > - It should be defined for RMII interface. > > -Both delay properties need to be a multiple of 170 for RGMII > > interface, > > -or will round down. Range 0~31*170. > > -Both delay properties need to be a multiple of 550 for MII/RMII > > interface, > > -or will round down. Range 0~31*550. > > - > > -- mediatek,rmii-rxc: boolean property, if present indicates that > > the RMII > > - reference clock, which is from external PHYs, is connected to > > RXC pin > > - on MT2712 SoC. > > - Otherwise, is connected to TXC pin. > > -- mediatek,rmii-clk-from-mac: boolean property, if present > > indicates that > > - MT2712 SoC provides the RMII reference clock, which outputs to > > TXC pin only. > > -- mediatek,txc-inverse: boolean property, if present indicates > > that > > - 1. tx clock will be inversed in MII/RGMII case, > > - 2. tx clock inside MAC will be inversed relative to reference > > clock > > - which is from external PHYs in RMII case, and it rarely > > happen. > > - 3. the reference clock, which outputs to TXC pin will be > > inversed in RMII case > > - when the reference clock is from MT2712 SoC. > > -- mediatek,rxc-inverse: boolean property, if present indicates > > that > > - 1. rx clock will be inversed in MII/RGMII case. > > - 2. reference clock will be inversed when arrived at MAC in RMII > > case, when > > - the reference clock is from external PHYs. > > - 3. the inside clock, which be sent to MAC, will be inversed in > > RMII case when > > - the reference clock is from MT2712 SoC. > > -- assigned-clocks: mac_main and ptp_ref clocks > > -- assigned-clock-parents: parent clocks of the assigned clocks > > - > > -Example: > > - eth: ethernet@1101c000 { > > - compatible = "mediatek,mt2712-gmac"; > > - reg = <0 0x1101c000 0 0x1300>; > > - interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_LOW>; > > - interrupt-names = "macirq"; > > - phy-mode ="rgmii-rxid"; > > - mac-address = [00 55 7b b5 7d f7]; > > - clock-names = "axi", > > - "apb", > > - "mac_main", > > - "ptp_ref", > > - "rmii_internal"; > > - clocks = <&pericfg CLK_PERI_GMAC>, > > - <&pericfg CLK_PERI_GMAC_PCLK>, > > - <&topckgen CLK_TOP_ETHER_125M_SEL>, > > - <&topckgen CLK_TOP_ETHER_50M_SEL>, > > - <&topckgen CLK_TOP_ETHER_50M_RMII_SEL>; > > - assigned-clocks = <&topckgen CLK_TOP_ETHER_125M_SEL>, > > - <&topckgen CLK_TOP_ETHER_50M_SEL>, > > - <&topckgen > > CLK_TOP_ETHER_50M_RMII_SEL>; > > - assigned-clock-parents = <&topckgen > > CLK_TOP_ETHERPLL_125M>, > > - <&topckgen CLK_TOP_APLL1_D3>, > > - <&topckgen > > CLK_TOP_ETHERPLL_50M>; > > - power-domains = <&scpsys MT2712_POWER_DOMAIN_AUDIO>; > > - mediatek,pericfg = <&pericfg>; > > - mediatek,tx-delay-ps = <1530>; > > - mediatek,rx-delay-ps = <1530>; > > - mediatek,rmii-rxc; > > - mediatek,txc-inverse; > > - mediatek,rxc-inverse; > > - snps,txpbl = <1>; > > - snps,rxpbl = <1>; > > - snps,reset-gpio = <&pio 87 GPIO_ACTIVE_LOW>; > > - snps,reset-active-low; > > - }; > > diff --git a/Documentation/devicetree/bindings/net/mediatek- > > dwmac.yaml b/Documentation/devicetree/bindings/net/mediatek- > > dwmac.yaml > > new file mode 100644 > > index 000000000000..9207266a6e69 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/net/mediatek-dwmac.yaml > > @@ -0,0 +1,156 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/net/mediatek-dwmac.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: MediaTek DWMAC glue layer controller > > + > > +maintainers: > > + - Biao Huang <biao.huang@mediatek.com> > > + > > +description: > > + This file documents platform glue layer for stmmac. > > + > > +# We need a select here so we don't match all nodes with > > 'snps,dwmac' > > +select: > > + properties: > > + compatible: > > + contains: > > + enum: > > + - mediatek,mt2712-gmac > > + required: > > + - compatible > > + > > +allOf: > > + - $ref: "snps,dwmac.yaml#" > > + > > +properties: > > + compatible: > > + oneOf: > > + - items: > > Don't need oneOf for 1 entry. OK, I'll fix it in next send. > > > + - enum: > > + - mediatek,mt2712-gmac > > + - const: snps,dwmac-4.20a > > + > > + clocks: > > + items: > > + - description: AXI clock > > + - description: APB clock > > + - description: MAC Main clock > > + - description: PTP clock > > + - description: RMII reference clock provided by MAC > > Seems you need 'minItems: 4' or are the DT files wrong? The current eth device node in mt2712.dtsi should be updated, and there is a patch in this series for it: "[PATCH net-next v8 3/6] arm64: dts: mt2712: update ethernet device node" > > > + > > + clock-names: > > + items: > > + - const: axi > > + - const: apb > > + - const: mac_main > > + - const: ptp_ref > > + - const: rmii_internal > > + > > + mediatek,pericfg: > > + $ref: /schemas/types.yaml#/definitions/phandle > > + description: > > + The phandle to the syscon node that control ethernet > > + interface and timing delay. > > + > > + mediatek,tx-delay-ps: > > + description: > > + The internal TX clock delay (provided by this driver) in > > nanoseconds. > > + For MT2712 RGMII interface, Allowed value need to be a > > multiple of 170, > > + or will round down. Range 0~31*170. > > + For MT2712 RMII/MII interface, Allowed value need to be a > > multiple of 550, > > + or will round down. Range 0~31*550. > > + > > + mediatek,rx-delay-ps: > > + description: > > + The internal RX clock delay (provided by this driver) in > > nanoseconds. > > + For MT2712 RGMII interface, Allowed value need to be a > > multiple of 170, > > + or will round down. Range 0~31*170. > > + For MT2712 RMII/MII interface, Allowed value need to be a > > multiple of 550, > > + or will round down. Range 0~31*550. > > + > > + mediatek,rmii-rxc: > > + type: boolean > > + description: > > + If present, indicates that the RMII reference clock, which > > is from external > > + PHYs, is connected to RXC pin. Otherwise, is connected to > > TXC pin. > > + > > + mediatek,rmii-clk-from-mac: > > + type: boolean > > + description: > > + If present, indicates that MAC provides the RMII reference > > clock, which > > + outputs to TXC pin only. > > + > > + mediatek,txc-inverse: > > + type: boolean > > + description: > > + If present, indicates that > > + 1. tx clock will be inversed in MII/RGMII case, > > + 2. tx clock inside MAC will be inversed relative to > > reference clock > > + which is from external PHYs in RMII case, and it rarely > > happen. > > + 3. the reference clock, which outputs to TXC pin will be > > inversed in RMII case > > + when the reference clock is from MAC. > > + > > + mediatek,rxc-inverse: > > + type: boolean > > + description: > > + If present, indicates that > > + 1. rx clock will be inversed in MII/RGMII case. > > + 2. reference clock will be inversed when arrived at MAC in > > RMII case, when > > + the reference clock is from external PHYs. > > + 3. the inside clock, which be sent to MAC, will be inversed > > in RMII case when > > + the reference clock is from MAC. > > + > > +required: > > + - compatible > > + - reg > > + - interrupts > > + - interrupt-names > > + - clocks > > + - clock-names > > + - phy-mode > > + - mediatek,pericfg > > + > > +unevaluatedProperties: false > > + > > +examples: > > + - | > > + #include <dt-bindings/clock/mt2712-clk.h> > > + #include <dt-bindings/gpio/gpio.h> > > + #include <dt-bindings/interrupt-controller/arm-gic.h> > > + #include <dt-bindings/interrupt-controller/irq.h> > > + #include <dt-bindings/power/mt2712-power.h> > > + > > + eth: ethernet@1101c000 { > > + compatible = "mediatek,mt2712-gmac", "snps,dwmac-4.20a"; > > + reg = <0x1101c000 0x1300>; > > + interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_LOW>; > > + interrupt-names = "macirq"; > > + phy-mode ="rgmii-rxid"; > > + mac-address = [00 55 7b b5 7d f7]; > > + clock-names = "axi", > > + "apb", > > + "mac_main", > > + "ptp_ref", > > + "rmii_internal"; > > + clocks = <&pericfg CLK_PERI_GMAC>, > > + <&pericfg CLK_PERI_GMAC_PCLK>, > > + <&topckgen CLK_TOP_ETHER_125M_SEL>, > > + <&topckgen CLK_TOP_ETHER_50M_SEL>, > > + <&topckgen CLK_TOP_ETHER_50M_RMII_SEL>; > > + assigned-clocks = <&topckgen CLK_TOP_ETHER_125M_SEL>, > > + <&topckgen CLK_TOP_ETHER_50M_SEL>, > > + <&topckgen CLK_TOP_ETHER_50M_RMII_SEL>; > > + assigned-clock-parents = <&topckgen > > CLK_TOP_ETHERPLL_125M>, > > + <&topckgen CLK_TOP_APLL1_D3>, > > + <&topckgen CLK_TOP_ETHERPLL_50M>; > > + power-domains = <&scpsys MT2712_POWER_DOMAIN_AUDIO>; > > + mediatek,pericfg = <&pericfg>; > > + mediatek,tx-delay-ps = <1530>; > > + snps,txpbl = <1>; > > + snps,rxpbl = <1>; > > + snps,reset-gpio = <&pio 87 GPIO_ACTIVE_LOW>; > > + snps,reset-delays-us = <0 10000 10000>; > > + }; > > -- > > 2.25.1 > > > >
diff --git a/Documentation/devicetree/bindings/net/mediatek-dwmac.txt b/Documentation/devicetree/bindings/net/mediatek-dwmac.txt deleted file mode 100644 index afbcaebf062e..000000000000 --- a/Documentation/devicetree/bindings/net/mediatek-dwmac.txt +++ /dev/null @@ -1,91 +0,0 @@ -MediaTek DWMAC glue layer controller - -This file documents platform glue layer for stmmac. -Please see stmmac.txt for the other unchanged properties. - -The device node has following properties. - -Required properties: -- compatible: Should be "mediatek,mt2712-gmac" for MT2712 SoC -- reg: Address and length of the register set for the device -- interrupts: Should contain the MAC interrupts -- interrupt-names: Should contain a list of interrupt names corresponding to - the interrupts in the interrupts property, if available. - Should be "macirq" for the main MAC IRQ -- clocks: Must contain a phandle for each entry in clock-names. -- clock-names: The name of the clock listed in the clocks property. These are - "axi", "apb", "mac_main", "ptp_ref", "rmii_internal" for MT2712 SoC. -- mac-address: See ethernet.txt in the same directory -- phy-mode: See ethernet.txt in the same directory -- mediatek,pericfg: A phandle to the syscon node that control ethernet - interface and timing delay. - -Optional properties: -- mediatek,tx-delay-ps: TX clock delay macro value. Default is 0. - It should be defined for RGMII/MII interface. - It should be defined for RMII interface when the reference clock is from MT2712 SoC. -- mediatek,rx-delay-ps: RX clock delay macro value. Default is 0. - It should be defined for RGMII/MII interface. - It should be defined for RMII interface. -Both delay properties need to be a multiple of 170 for RGMII interface, -or will round down. Range 0~31*170. -Both delay properties need to be a multiple of 550 for MII/RMII interface, -or will round down. Range 0~31*550. - -- mediatek,rmii-rxc: boolean property, if present indicates that the RMII - reference clock, which is from external PHYs, is connected to RXC pin - on MT2712 SoC. - Otherwise, is connected to TXC pin. -- mediatek,rmii-clk-from-mac: boolean property, if present indicates that - MT2712 SoC provides the RMII reference clock, which outputs to TXC pin only. -- mediatek,txc-inverse: boolean property, if present indicates that - 1. tx clock will be inversed in MII/RGMII case, - 2. tx clock inside MAC will be inversed relative to reference clock - which is from external PHYs in RMII case, and it rarely happen. - 3. the reference clock, which outputs to TXC pin will be inversed in RMII case - when the reference clock is from MT2712 SoC. -- mediatek,rxc-inverse: boolean property, if present indicates that - 1. rx clock will be inversed in MII/RGMII case. - 2. reference clock will be inversed when arrived at MAC in RMII case, when - the reference clock is from external PHYs. - 3. the inside clock, which be sent to MAC, will be inversed in RMII case when - the reference clock is from MT2712 SoC. -- assigned-clocks: mac_main and ptp_ref clocks -- assigned-clock-parents: parent clocks of the assigned clocks - -Example: - eth: ethernet@1101c000 { - compatible = "mediatek,mt2712-gmac"; - reg = <0 0x1101c000 0 0x1300>; - interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_LOW>; - interrupt-names = "macirq"; - phy-mode ="rgmii-rxid"; - mac-address = [00 55 7b b5 7d f7]; - clock-names = "axi", - "apb", - "mac_main", - "ptp_ref", - "rmii_internal"; - clocks = <&pericfg CLK_PERI_GMAC>, - <&pericfg CLK_PERI_GMAC_PCLK>, - <&topckgen CLK_TOP_ETHER_125M_SEL>, - <&topckgen CLK_TOP_ETHER_50M_SEL>, - <&topckgen CLK_TOP_ETHER_50M_RMII_SEL>; - assigned-clocks = <&topckgen CLK_TOP_ETHER_125M_SEL>, - <&topckgen CLK_TOP_ETHER_50M_SEL>, - <&topckgen CLK_TOP_ETHER_50M_RMII_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_ETHERPLL_125M>, - <&topckgen CLK_TOP_APLL1_D3>, - <&topckgen CLK_TOP_ETHERPLL_50M>; - power-domains = <&scpsys MT2712_POWER_DOMAIN_AUDIO>; - mediatek,pericfg = <&pericfg>; - mediatek,tx-delay-ps = <1530>; - mediatek,rx-delay-ps = <1530>; - mediatek,rmii-rxc; - mediatek,txc-inverse; - mediatek,rxc-inverse; - snps,txpbl = <1>; - snps,rxpbl = <1>; - snps,reset-gpio = <&pio 87 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - }; diff --git a/Documentation/devicetree/bindings/net/mediatek-dwmac.yaml b/Documentation/devicetree/bindings/net/mediatek-dwmac.yaml new file mode 100644 index 000000000000..9207266a6e69 --- /dev/null +++ b/Documentation/devicetree/bindings/net/mediatek-dwmac.yaml @@ -0,0 +1,156 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/mediatek-dwmac.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek DWMAC glue layer controller + +maintainers: + - Biao Huang <biao.huang@mediatek.com> + +description: + This file documents platform glue layer for stmmac. + +# We need a select here so we don't match all nodes with 'snps,dwmac' +select: + properties: + compatible: + contains: + enum: + - mediatek,mt2712-gmac + required: + - compatible + +allOf: + - $ref: "snps,dwmac.yaml#" + +properties: + compatible: + oneOf: + - items: + - enum: + - mediatek,mt2712-gmac + - const: snps,dwmac-4.20a + + clocks: + items: + - description: AXI clock + - description: APB clock + - description: MAC Main clock + - description: PTP clock + - description: RMII reference clock provided by MAC + + clock-names: + items: + - const: axi + - const: apb + - const: mac_main + - const: ptp_ref + - const: rmii_internal + + mediatek,pericfg: + $ref: /schemas/types.yaml#/definitions/phandle + description: + The phandle to the syscon node that control ethernet + interface and timing delay. + + mediatek,tx-delay-ps: + description: + The internal TX clock delay (provided by this driver) in nanoseconds. + For MT2712 RGMII interface, Allowed value need to be a multiple of 170, + or will round down. Range 0~31*170. + For MT2712 RMII/MII interface, Allowed value need to be a multiple of 550, + or will round down. Range 0~31*550. + + mediatek,rx-delay-ps: + description: + The internal RX clock delay (provided by this driver) in nanoseconds. + For MT2712 RGMII interface, Allowed value need to be a multiple of 170, + or will round down. Range 0~31*170. + For MT2712 RMII/MII interface, Allowed value need to be a multiple of 550, + or will round down. Range 0~31*550. + + mediatek,rmii-rxc: + type: boolean + description: + If present, indicates that the RMII reference clock, which is from external + PHYs, is connected to RXC pin. Otherwise, is connected to TXC pin. + + mediatek,rmii-clk-from-mac: + type: boolean + description: + If present, indicates that MAC provides the RMII reference clock, which + outputs to TXC pin only. + + mediatek,txc-inverse: + type: boolean + description: + If present, indicates that + 1. tx clock will be inversed in MII/RGMII case, + 2. tx clock inside MAC will be inversed relative to reference clock + which is from external PHYs in RMII case, and it rarely happen. + 3. the reference clock, which outputs to TXC pin will be inversed in RMII case + when the reference clock is from MAC. + + mediatek,rxc-inverse: + type: boolean + description: + If present, indicates that + 1. rx clock will be inversed in MII/RGMII case. + 2. reference clock will be inversed when arrived at MAC in RMII case, when + the reference clock is from external PHYs. + 3. the inside clock, which be sent to MAC, will be inversed in RMII case when + the reference clock is from MAC. + +required: + - compatible + - reg + - interrupts + - interrupt-names + - clocks + - clock-names + - phy-mode + - mediatek,pericfg + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/mt2712-clk.h> + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/power/mt2712-power.h> + + eth: ethernet@1101c000 { + compatible = "mediatek,mt2712-gmac", "snps,dwmac-4.20a"; + reg = <0x1101c000 0x1300>; + interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "macirq"; + phy-mode ="rgmii-rxid"; + mac-address = [00 55 7b b5 7d f7]; + clock-names = "axi", + "apb", + "mac_main", + "ptp_ref", + "rmii_internal"; + clocks = <&pericfg CLK_PERI_GMAC>, + <&pericfg CLK_PERI_GMAC_PCLK>, + <&topckgen CLK_TOP_ETHER_125M_SEL>, + <&topckgen CLK_TOP_ETHER_50M_SEL>, + <&topckgen CLK_TOP_ETHER_50M_RMII_SEL>; + assigned-clocks = <&topckgen CLK_TOP_ETHER_125M_SEL>, + <&topckgen CLK_TOP_ETHER_50M_SEL>, + <&topckgen CLK_TOP_ETHER_50M_RMII_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_ETHERPLL_125M>, + <&topckgen CLK_TOP_APLL1_D3>, + <&topckgen CLK_TOP_ETHERPLL_50M>; + power-domains = <&scpsys MT2712_POWER_DOMAIN_AUDIO>; + mediatek,pericfg = <&pericfg>; + mediatek,tx-delay-ps = <1530>; + snps,txpbl = <1>; + snps,rxpbl = <1>; + snps,reset-gpio = <&pio 87 GPIO_ACTIVE_LOW>; + snps,reset-delays-us = <0 10000 10000>; + };
Convert mediatek-dwmac to DT schema, and delete old mediatek-dwmac.txt. And there are some changes in .yaml than .txt, others almost keep the same: 1. compatible "const: snps,dwmac-4.20". 2. delete "snps,reset-active-low;" in example, since driver remove this property long ago. 3. add "snps,reset-delay-us = <0 10000 10000>" in example. 4. the example is for rgmii interface, keep related properties only. Signed-off-by: Biao Huang <biao.huang@mediatek.com> --- .../bindings/net/mediatek-dwmac.txt | 91 ---------- .../bindings/net/mediatek-dwmac.yaml | 156 ++++++++++++++++++ 2 files changed, 156 insertions(+), 91 deletions(-) delete mode 100644 Documentation/devicetree/bindings/net/mediatek-dwmac.txt create mode 100644 Documentation/devicetree/bindings/net/mediatek-dwmac.yaml