| Message ID | 20211212191541.2148178-1-dev@lynxeye.de (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | arm64: dts: imx8mq: disable DDRC node by default | expand |
Hi Lucas, On Sun, Dec 12, 2021 at 4:16 PM Lucas Stach <dev@lynxeye.de> wrote: > > Without a OPP table or a downstream TF-A running on the system the DDRC will > fail to probe, as it has no means to scale the DRAM frequency in that case. > This however will block the bus scaling driver to come up and this in turn > prevents other devices that hook into the interconnect from probing. > > If the DDRC is disabled, the interconnect driver will simply ignore it. As > most systems don't want to scale the DRAM frequency, disable the node by > default and only enable it on the systems that actually uses this > capability and provides a valid OPP table in the DT. > > Signed-off-by: Lucas Stach <dev@lynxeye.de> Reviewed-by: Fabio Estevam <festevam@gmail.com> Should we do the same on imx8mm too?
Am Sonntag, dem 12.12.2021 um 20:15 +0100 schrieb Lucas Stach: > Without a OPP table or a downstream TF-A running on the system the > DDRC will > fail to probe, as it has no means to scale the DRAM frequency in that > case. > This however will block the bus scaling driver to come up and this in > turn > prevents other devices that hook into the interconnect from probing. > > If the DDRC is disabled, the interconnect driver will simply ignore > it. As > most systems don't want to scale the DRAM frequency, disable the node > by > default and only enable it on the systems that actually uses this > capability and provides a valid OPP table in the DT. > > Signed-off-by: Lucas Stach <dev@lynxeye.de> > Acked-by: Martin Kepplinger <martin.kepplinger@puri.sm> but I'd like to append a question to NXP who afaik implemented devfreq depending on "downstream TF-A" for imx8m: How are your plans to add support to mainline TF-A? thank you! martin > --- > arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 1 + > arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi | 1 + > arch/arm64/boot/dts/freescale/imx8mq.dtsi | 1 + > 3 files changed, 3 insertions(+) > > diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts > b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts > index b83df77195ec..e989a9e450ed 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts > +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts > @@ -122,6 +122,7 @@ &A53_3 { > }; > > &ddrc { > + status = "okay"; > operating-points-v2 = <&ddrc_opp_table>; > > ddrc_opp_table: opp-table { > diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi > b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi > index 60d47c71499b..5c0e98c36f94 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi > @@ -238,6 +238,7 @@ &A53_3 { > }; > > &ddrc { > + status = "okay"; > operating-points-v2 = <&ddrc_opp_table>; > > ddrc_opp_table: opp-table { > diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi > b/arch/arm64/boot/dts/freescale/imx8mq.dtsi > index 972766b67a15..f5af9765e239 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi > @@ -1554,6 +1554,7 @@ ddrc: memory-controller@3d400000 { > <&clk IMX8MQ_DRAM_PLL_OUT>, > <&clk IMX8MQ_CLK_DRAM_ALT>, > <&clk IMX8MQ_CLK_DRAM_APB>; > + status = "disabled"; > }; > > ddr-pmu@3d800000 {
Hi, On Sun, Dec 12, 2021 at 08:15:41PM +0100, Lucas Stach wrote: > Without a OPP table or a downstream TF-A running on the system the DDRC will > fail to probe, as it has no means to scale the DRAM frequency in that case. > This however will block the bus scaling driver to come up and this in turn > prevents other devices that hook into the interconnect from probing. > > If the DDRC is disabled, the interconnect driver will simply ignore it. As > most systems don't want to scale the DRAM frequency, disable the node by > default and only enable it on the systems that actually uses this > capability and provides a valid OPP table in the DT. > > Signed-off-by: Lucas Stach <dev@lynxeye.de> > --- > arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 1 + > arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi | 1 + > arch/arm64/boot/dts/freescale/imx8mq.dtsi | 1 + > 3 files changed, 3 insertions(+) > > diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts > index b83df77195ec..e989a9e450ed 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts > +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts > @@ -122,6 +122,7 @@ &A53_3 { > }; > > &ddrc { > + status = "okay"; > operating-points-v2 = <&ddrc_opp_table>; > > ddrc_opp_table: opp-table { > diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi > index 60d47c71499b..5c0e98c36f94 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi > @@ -238,6 +238,7 @@ &A53_3 { > }; > > &ddrc { > + status = "okay"; > operating-points-v2 = <&ddrc_opp_table>; > > ddrc_opp_table: opp-table { > diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi > index 972766b67a15..f5af9765e239 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi > @@ -1554,6 +1554,7 @@ ddrc: memory-controller@3d400000 { > <&clk IMX8MQ_DRAM_PLL_OUT>, > <&clk IMX8MQ_CLK_DRAM_ALT>, > <&clk IMX8MQ_CLK_DRAM_APB>; > + status = "disabled"; > }; > > ddr-pmu@3d800000 { Reviewed-by: Guido Günther <agx@sigxcpu.org> Cheers, -- Guido > -- > 2.31.1 >
Am Sonntag, dem 12.12.2021 um 16:29 -0300 schrieb Fabio Estevam: > Hi Lucas, > > On Sun, Dec 12, 2021 at 4:16 PM Lucas Stach <dev@lynxeye.de> wrote: > > > > Without a OPP table or a downstream TF-A running on the system the DDRC will > > fail to probe, as it has no means to scale the DRAM frequency in that case. > > This however will block the bus scaling driver to come up and this in turn > > prevents other devices that hook into the interconnect from probing. > > > > If the DDRC is disabled, the interconnect driver will simply ignore it. As > > most systems don't want to scale the DRAM frequency, disable the node by > > default and only enable it on the systems that actually uses this > > capability and provides a valid OPP table in the DT. > > > > Signed-off-by: Lucas Stach <dev@lynxeye.de> > > Reviewed-by: Fabio Estevam <festevam@gmail.com> > > Should we do the same on imx8mm too? Not sure, with the i.MX8MM there are a lot more systems that are providing a valid OPP table. Also I don't see the interconnect being hooked up to devices in the i.MX8MM DT, so a non-function interconnect driver, will at least not block other devices as is the case with the i.MX8MQ. However, there still is the issue that all those systems those depend on a downstream TF-A running on the system, as upstream TF-A has no support for scaling the DDR frequency. Regards, Lucas
On Sun, Dec 12, 2021 at 08:15:41PM +0100, Lucas Stach wrote: > Without a OPP table or a downstream TF-A running on the system the DDRC will > fail to probe, as it has no means to scale the DRAM frequency in that case. > This however will block the bus scaling driver to come up and this in turn > prevents other devices that hook into the interconnect from probing. > > If the DDRC is disabled, the interconnect driver will simply ignore it. As > most systems don't want to scale the DRAM frequency, disable the node by > default and only enable it on the systems that actually uses this > capability and provides a valid OPP table in the DT. > > Signed-off-by: Lucas Stach <dev@lynxeye.de> > --- > arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 1 + > arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi | 1 + > arch/arm64/boot/dts/freescale/imx8mq.dtsi | 1 + > 3 files changed, 3 insertions(+) > > diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts > index b83df77195ec..e989a9e450ed 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts > +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts > @@ -122,6 +122,7 @@ &A53_3 { > }; > > &ddrc { > + status = "okay"; Please move it to end of property list. Shawn > operating-points-v2 = <&ddrc_opp_table>; > > ddrc_opp_table: opp-table { > diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi > index 60d47c71499b..5c0e98c36f94 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi > @@ -238,6 +238,7 @@ &A53_3 { > }; > > &ddrc { > + status = "okay"; > operating-points-v2 = <&ddrc_opp_table>; > > ddrc_opp_table: opp-table { > diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi > index 972766b67a15..f5af9765e239 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi > @@ -1554,6 +1554,7 @@ ddrc: memory-controller@3d400000 { > <&clk IMX8MQ_DRAM_PLL_OUT>, > <&clk IMX8MQ_CLK_DRAM_ALT>, > <&clk IMX8MQ_CLK_DRAM_APB>; > + status = "disabled"; > }; > > ddr-pmu@3d800000 { > -- > 2.31.1 >
diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts index b83df77195ec..e989a9e450ed 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts @@ -122,6 +122,7 @@ &A53_3 { }; &ddrc { + status = "okay"; operating-points-v2 = <&ddrc_opp_table>; ddrc_opp_table: opp-table { diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi index 60d47c71499b..5c0e98c36f94 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi @@ -238,6 +238,7 @@ &A53_3 { }; &ddrc { + status = "okay"; operating-points-v2 = <&ddrc_opp_table>; ddrc_opp_table: opp-table { diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index 972766b67a15..f5af9765e239 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -1554,6 +1554,7 @@ ddrc: memory-controller@3d400000 { <&clk IMX8MQ_DRAM_PLL_OUT>, <&clk IMX8MQ_CLK_DRAM_ALT>, <&clk IMX8MQ_CLK_DRAM_APB>; + status = "disabled"; }; ddr-pmu@3d800000 {
Without a OPP table or a downstream TF-A running on the system the DDRC will fail to probe, as it has no means to scale the DRAM frequency in that case. This however will block the bus scaling driver to come up and this in turn prevents other devices that hook into the interconnect from probing. If the DDRC is disabled, the interconnect driver will simply ignore it. As most systems don't want to scale the DRAM frequency, disable the node by default and only enable it on the systems that actually uses this capability and provides a valid OPP table in the DT. Signed-off-by: Lucas Stach <dev@lynxeye.de> --- arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 1 + arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi | 1 + arch/arm64/boot/dts/freescale/imx8mq.dtsi | 1 + 3 files changed, 3 insertions(+)