| Message ID | 20211213152208.290923-1-luca.weiss@fairphone.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | dt-bindings: qcom,pdc: convert to YAML | expand |
On Mon, 13 Dec 2021 16:22:08 +0100, Luca Weiss wrote: > Convert the PDC interrupt controller bindings to YAML. > > Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> > --- > This patch depends on the following patch, which fixed sm8250 & sm8350 > compatibles and adds sm6350. > https://lore.kernel.org/linux-arm-msm/20211213082614.22651-4-luca.weiss@fairphone.com/ > > Also, if somebody has a better suggestion for the register names, > the second one is pulled from downstream commit message which calls it > both "SPI config registers" and "interface registers": > https://source.codeaurora.org/quic/la/kernel/msm-4.19/commit/?id=cdefb63745e051a5bcf69663ac9d084d7da1eeec > > .../interrupt-controller/qcom,pdc.txt | 77 ----------------- > .../interrupt-controller/qcom,pdc.yaml | 86 +++++++++++++++++++ > 2 files changed, 86 insertions(+), 77 deletions(-) > delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt > create mode 100644 Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml > Reviewed-by: Rob Herring <robh@kernel.org>
Hi Luca, On 12/13/2021 8:52 PM, Luca Weiss wrote: > Convert the PDC interrupt controller bindings to YAML. > > Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> > --- > This patch depends on the following patch, which fixed sm8250 & sm8350 > compatibles and adds sm6350. > https://lore.kernel.org/linux-arm-msm/20211213082614.22651-4-luca.weiss@fairphone.com/ > > Also, if somebody has a better suggestion for the register names, > the second one is pulled from downstream commit message which calls it > both "SPI config registers" and "interface registers": > https://source.codeaurora.org/quic/la/kernel/msm-4.19/commit/?id=cdefb63745e051a5bcf69663ac9d084d7da1eeec Thanks for the patch. Please use "apss-shared-spi-cfg" name for the second reg. It was intended in [1] to remove it since there are no user in upstream for second reg. but it should be fine to convert existing to yaml first and then look to fix that. [1] https://patchwork.kernel.org/project/linux-arm-msm/list/?series=449725&state=%2A&archive=both [2] https://patchwork.kernel.org/project/linux-arm-msm/patch/1616409015-27682-1-git-send-email-mkshah@codeaurora.org/ Thanks, Maulik > > .../interrupt-controller/qcom,pdc.txt | 77 ----------------- > .../interrupt-controller/qcom,pdc.yaml | 86 +++++++++++++++++++ > 2 files changed, 86 insertions(+), 77 deletions(-) > delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt > create mode 100644 Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml >
Hi Maulik, On Mon Dec 20, 2021 at 1:24 PM CET, Maulik Shah wrote: > Hi Luca, > > On 12/13/2021 8:52 PM, Luca Weiss wrote: > > Convert the PDC interrupt controller bindings to YAML. > > > > Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> > > --- > > This patch depends on the following patch, which fixed sm8250 & sm8350 > > compatibles and adds sm6350. > > https://lore.kernel.org/linux-arm-msm/20211213082614.22651-4-luca.weiss@fairphone.com/ > > > > Also, if somebody has a better suggestion for the register names, > > the second one is pulled from downstream commit message which calls it > > both "SPI config registers" and "interface registers": > > https://source.codeaurora.org/quic/la/kernel/msm-4.19/commit/?id=cdefb63745e051a5bcf69663ac9d084d7da1eeec > > Thanks for the patch. Please use "apss-shared-spi-cfg" name for the > second reg. > > It was intended in [1] to remove it since there are no user in upstream > for second reg. but it should be fine to convert existing to yaml first > and then look to fix that. > Do you have a full-text version of that? I'd use it instead of this in the binding. - description: PDC interface register region "apss-shared-spi-cfg" sounds more appropriate for reg-names property that I don't plan on adding. Regards Luca > [1] > https://patchwork.kernel.org/project/linux-arm-msm/list/?series=449725&state=%2A&archive=both > > [2] > https://patchwork.kernel.org/project/linux-arm-msm/patch/1616409015-27682-1-git-send-email-mkshah@codeaurora.org/ > > Thanks, > Maulik > > > > .../interrupt-controller/qcom,pdc.txt | 77 ----------------- > > .../interrupt-controller/qcom,pdc.yaml | 86 +++++++++++++++++++ > > 2 files changed, 86 insertions(+), 77 deletions(-) > > delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt > > create mode 100644 Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml > >
Hi Luca, On 12/29/2021 3:11 PM, Luca Weiss wrote: > Hi Maulik, > > On Mon Dec 20, 2021 at 1:24 PM CET, Maulik Shah wrote: >> Hi Luca, >> >> On 12/13/2021 8:52 PM, Luca Weiss wrote: >>> Convert the PDC interrupt controller bindings to YAML. >>> >>> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> >>> --- >>> This patch depends on the following patch, which fixed sm8250 & sm8350 >>> compatibles and adds sm6350. >>> https://lore.kernel.org/linux-arm-msm/20211213082614.22651-4-luca.weiss@fairphone.com/ >>> >>> Also, if somebody has a better suggestion for the register names, >>> the second one is pulled from downstream commit message which calls it >>> both "SPI config registers" and "interface registers": >>> https://source.codeaurora.org/quic/la/kernel/msm-4.19/commit/?id=cdefb63745e051a5bcf69663ac9d084d7da1eeec >> Thanks for the patch. Please use "apss-shared-spi-cfg" name for the >> second reg. >> >> It was intended in [1] to remove it since there are no user in upstream >> for second reg. but it should be fine to convert existing to yaml first >> and then look to fix that. >> > Do you have a full-text version of that? I'd use it instead of this in > the binding. > > - description: PDC interface register region you can use below description, description: Edge or Level config register for SPI interrupts Thanks, Maulik
diff --git a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt deleted file mode 100644 index 3b7b1134dea9..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt +++ /dev/null @@ -1,77 +0,0 @@ -PDC interrupt controller - -Qualcomm Technologies Inc. SoCs based on the RPM Hardened architecture have a -Power Domain Controller (PDC) that is on always-on domain. In addition to -providing power control for the power domains, the hardware also has an -interrupt controller that can be used to help detect edge low interrupts as -well detect interrupts when the GIC is non-operational. - -GIC is parent interrupt controller at the highest level. Platform interrupt -controller PDC is next in hierarchy, followed by others. Drivers requiring -wakeup capabilities of their device interrupts routed through the PDC, must -specify PDC as their interrupt controller and request the PDC port associated -with the GIC interrupt. See example below. - -Properties: - -- compatible: - Usage: required - Value type: <string> - Definition: Should contain "qcom,<soc>-pdc" and "qcom,pdc" - - "qcom,sc7180-pdc": For SC7180 - - "qcom,sc7280-pdc": For SC7280 - - "qcom,sdm845-pdc": For SDM845 - - "qcom,sm6350-pdc": For SM6350 - - "qcom,sm8250-pdc": For SM8250 - - "qcom,sm8350-pdc": For SM8350 - -- reg: - Usage: required - Value type: <prop-encoded-array> - Definition: Specifies the base physical address for PDC hardware. - -- interrupt-cells: - Usage: required - Value type: <u32> - Definition: Specifies the number of cells needed to encode an interrupt - source. - Must be 2. - The first element of the tuple is the PDC pin for the - interrupt. - The second element is the trigger type. - -- interrupt-controller: - Usage: required - Value type: <bool> - Definition: Identifies the node as an interrupt controller. - -- qcom,pdc-ranges: - Usage: required - Value type: <u32 array> - Definition: Specifies the PDC pin offset and the number of PDC ports. - The tuples indicates the valid mapping of valid PDC ports - and their hwirq mapping. - The first element of the tuple is the starting PDC port. - The second element is the GIC hwirq number for the PDC port. - The third element is the number of interrupts in sequence. - -Example: - - pdc: interrupt-controller@b220000 { - compatible = "qcom,sdm845-pdc"; - reg = <0xb220000 0x30000>; - qcom,pdc-ranges = <0 512 94>, <94 641 15>, <115 662 7>; - #interrupt-cells = <2>; - interrupt-parent = <&intc>; - interrupt-controller; - }; - -DT binding of a device that wants to use the GIC SPI 514 as a wakeup -interrupt, must do - - - wake-device { - interrupts-extended = <&pdc 2 IRQ_TYPE_LEVEL_HIGH>; - }; - -In this case interrupt 514 would be mapped to port 2 on the PDC as defined by -the qcom,pdc-ranges property. diff --git a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml new file mode 100644 index 000000000000..8465d79945ca --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml @@ -0,0 +1,86 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/qcom,pdc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: PDC interrupt controller + +maintainers: + - Bjorn Andersson <bjorn.andersson@linaro.org> + +description: | + Qualcomm Technologies Inc. SoCs based on the RPM Hardened architecture have a + Power Domain Controller (PDC) that is on always-on domain. In addition to + providing power control for the power domains, the hardware also has an + interrupt controller that can be used to help detect edge low interrupts as + well detect interrupts when the GIC is non-operational. + + GIC is parent interrupt controller at the highest level. Platform interrupt + controller PDC is next in hierarchy, followed by others. Drivers requiring + wakeup capabilities of their device interrupts routed through the PDC, must + specify PDC as their interrupt controller and request the PDC port associated + with the GIC interrupt. See example below. + +properties: + compatible: + items: + - enum: + - qcom,sc7180-pdc + - qcom,sc7280-pdc + - qcom,sdm845-pdc + - qcom,sm6350-pdc + - qcom,sm8250-pdc + - qcom,sm8350-pdc + - const: qcom,pdc + + reg: + minItems: 1 + items: + - description: PDC base register region + - description: PDC interface register region + + '#interrupt-cells': + const: 2 + + interrupt-controller: true + + qcom,pdc-ranges: + $ref: /schemas/types.yaml#/definitions/uint32-matrix + minItems: 1 + maxItems: 32 # no hard limit + items: + items: + - description: starting PDC port + - description: GIC hwirq number for the PDC port + - description: number of interrupts in sequence + description: | + Specifies the PDC pin offset and the number of PDC ports. + The tuples indicates the valid mapping of valid PDC ports + and their hwirq mapping. + +required: + - compatible + - reg + - '#interrupt-cells' + - interrupt-controller + - qcom,pdc-ranges + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + + pdc: interrupt-controller@b220000 { + compatible = "qcom,sdm845-pdc", "qcom,pdc"; + reg = <0xb220000 0x30000>; + qcom,pdc-ranges = <0 512 94>, <94 641 15>, <115 662 7>; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupt-controller; + }; + + wake-device { + interrupts-extended = <&pdc 2 IRQ_TYPE_LEVEL_HIGH>; + };
Convert the PDC interrupt controller bindings to YAML. Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> --- This patch depends on the following patch, which fixed sm8250 & sm8350 compatibles and adds sm6350. https://lore.kernel.org/linux-arm-msm/20211213082614.22651-4-luca.weiss@fairphone.com/ Also, if somebody has a better suggestion for the register names, the second one is pulled from downstream commit message which calls it both "SPI config registers" and "interface registers": https://source.codeaurora.org/quic/la/kernel/msm-4.19/commit/?id=cdefb63745e051a5bcf69663ac9d084d7da1eeec .../interrupt-controller/qcom,pdc.txt | 77 ----------------- .../interrupt-controller/qcom,pdc.yaml | 86 +++++++++++++++++++ 2 files changed, 86 insertions(+), 77 deletions(-) delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt create mode 100644 Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml