| Message ID | 20220105022247.21131-4-frank.chang@sifive.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Fix RVV calling incorrect RFV/RVD check functions bug | expand |
On Wed, Jan 5, 2022 at 12:24 PM <frank.chang@sifive.com> wrote: > > From: Frank Chang <frank.chang@sifive.com> > > vfncvt.f.xu.w, vfncvt.f.x.w convert double-width integer to single-width > floating-point. Therefore, should use require_rvf() to check whether > RVF/RVD is enabled. > > vfncvt.f.f.w, vfncvt.rod.f.f.w convert double-width floating-point to > single-width integer. Therefore, should use require_scale_rvf() to check > whether RVF/RVD is enabled. > > Signed-off-by: Frank Chang <frank.chang@sifive.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/insn_trans/trans_rvv.c.inc | 32 ++++++++++++++++++------- > 1 file changed, 24 insertions(+), 8 deletions(-) > > diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc > index f1b44ccad2..6c285c958b 100644 > --- a/target/riscv/insn_trans/trans_rvv.c.inc > +++ b/target/riscv/insn_trans/trans_rvv.c.inc > @@ -2719,17 +2719,29 @@ GEN_OPFXV_WIDEN_TRANS(vfwcvt_f_x_v) > static bool opfv_narrow_check(DisasContext *s, arg_rmr *a) > { > return require_rvv(s) && > - require_rvf(s) && > - (s->sew != MO_64) && > vext_check_isa_ill(s) && > /* OPFV narrowing instructions ignore vs1 check */ > vext_check_sd(s, a->rd, a->rs2, a->vm); > } > > -#define GEN_OPFV_NARROW_TRANS(NAME, HELPER, FRM) \ > +static bool opfxv_narrow_check(DisasContext *s, arg_rmr *a) > +{ > + return opfv_narrow_check(s, a) && > + require_rvf(s) && > + (s->sew != MO_64); > +} > + > +static bool opffv_narrow_check(DisasContext *s, arg_rmr *a) > +{ > + return opfv_narrow_check(s, a) && > + require_scale_rvf(s) && > + (s->sew != MO_8); > +} > + > +#define GEN_OPFV_NARROW_TRANS(NAME, CHECK, HELPER, FRM) \ > static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ > { \ > - if (opfv_narrow_check(s, a)) { \ > + if (CHECK(s, a)) { \ > if (FRM != RISCV_FRM_DYN) { \ > gen_set_rm(s, RISCV_FRM_DYN); \ > } \ > @@ -2756,11 +2768,15 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ > return false; \ > } > > -GEN_OPFV_NARROW_TRANS(vfncvt_f_xu_w, vfncvt_f_xu_w, RISCV_FRM_DYN) > -GEN_OPFV_NARROW_TRANS(vfncvt_f_x_w, vfncvt_f_x_w, RISCV_FRM_DYN) > -GEN_OPFV_NARROW_TRANS(vfncvt_f_f_w, vfncvt_f_f_w, RISCV_FRM_DYN) > +GEN_OPFV_NARROW_TRANS(vfncvt_f_xu_w, opfxv_narrow_check, vfncvt_f_xu_w, > + RISCV_FRM_DYN) > +GEN_OPFV_NARROW_TRANS(vfncvt_f_x_w, opfxv_narrow_check, vfncvt_f_x_w, > + RISCV_FRM_DYN) > +GEN_OPFV_NARROW_TRANS(vfncvt_f_f_w, opffv_narrow_check, vfncvt_f_f_w, > + RISCV_FRM_DYN) > /* Reuse the helper function from vfncvt.f.f.w */ > -GEN_OPFV_NARROW_TRANS(vfncvt_rod_f_f_w, vfncvt_f_f_w, RISCV_FRM_ROD) > +GEN_OPFV_NARROW_TRANS(vfncvt_rod_f_f_w, opffv_narrow_check, vfncvt_f_f_w, > + RISCV_FRM_ROD) > > static bool opxfv_narrow_check(DisasContext *s, arg_rmr *a) > { > -- > 2.31.1 > >
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index f1b44ccad2..6c285c958b 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -2719,17 +2719,29 @@ GEN_OPFXV_WIDEN_TRANS(vfwcvt_f_x_v) static bool opfv_narrow_check(DisasContext *s, arg_rmr *a) { return require_rvv(s) && - require_rvf(s) && - (s->sew != MO_64) && vext_check_isa_ill(s) && /* OPFV narrowing instructions ignore vs1 check */ vext_check_sd(s, a->rd, a->rs2, a->vm); } -#define GEN_OPFV_NARROW_TRANS(NAME, HELPER, FRM) \ +static bool opfxv_narrow_check(DisasContext *s, arg_rmr *a) +{ + return opfv_narrow_check(s, a) && + require_rvf(s) && + (s->sew != MO_64); +} + +static bool opffv_narrow_check(DisasContext *s, arg_rmr *a) +{ + return opfv_narrow_check(s, a) && + require_scale_rvf(s) && + (s->sew != MO_8); +} + +#define GEN_OPFV_NARROW_TRANS(NAME, CHECK, HELPER, FRM) \ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ { \ - if (opfv_narrow_check(s, a)) { \ + if (CHECK(s, a)) { \ if (FRM != RISCV_FRM_DYN) { \ gen_set_rm(s, RISCV_FRM_DYN); \ } \ @@ -2756,11 +2768,15 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ return false; \ } -GEN_OPFV_NARROW_TRANS(vfncvt_f_xu_w, vfncvt_f_xu_w, RISCV_FRM_DYN) -GEN_OPFV_NARROW_TRANS(vfncvt_f_x_w, vfncvt_f_x_w, RISCV_FRM_DYN) -GEN_OPFV_NARROW_TRANS(vfncvt_f_f_w, vfncvt_f_f_w, RISCV_FRM_DYN) +GEN_OPFV_NARROW_TRANS(vfncvt_f_xu_w, opfxv_narrow_check, vfncvt_f_xu_w, + RISCV_FRM_DYN) +GEN_OPFV_NARROW_TRANS(vfncvt_f_x_w, opfxv_narrow_check, vfncvt_f_x_w, + RISCV_FRM_DYN) +GEN_OPFV_NARROW_TRANS(vfncvt_f_f_w, opffv_narrow_check, vfncvt_f_f_w, + RISCV_FRM_DYN) /* Reuse the helper function from vfncvt.f.f.w */ -GEN_OPFV_NARROW_TRANS(vfncvt_rod_f_f_w, vfncvt_f_f_w, RISCV_FRM_ROD) +GEN_OPFV_NARROW_TRANS(vfncvt_rod_f_f_w, opffv_narrow_check, vfncvt_f_f_w, + RISCV_FRM_ROD) static bool opxfv_narrow_check(DisasContext *s, arg_rmr *a) {