| Message ID | 20220105225013.1567871-3-lizhi.hou@xilinx.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | XRT Alveo driver infrastructure overview | expand |
On 1/5/22 2:50 PM, Lizhi Hou wrote: > Create device tree binding document for partitions and pr isolation on > Xilinx Alveo platform. > > Signed-off-by: Sonal Santan <sonal.santan@xilinx.com> > Signed-off-by: Max Zhen <max.zhen@xilinx.com> > Signed-off-by: Lizhi Hou <lizhi.hou@xilinx.com> > --- > .../bindings/fpga/xlnx,alveo-partition.yaml | 76 +++++++++++++++++++ > .../fpga/xlnx,alveo-pr-isolation.yaml | 40 ++++++++++ > 2 files changed, 116 insertions(+) > create mode 100644 Documentation/devicetree/bindings/fpga/xlnx,alveo-partition.yaml > create mode 100644 Documentation/devicetree/bindings/fpga/xlnx,alveo-pr-isolation.yaml > > diff --git a/Documentation/devicetree/bindings/fpga/xlnx,alveo-partition.yaml b/Documentation/devicetree/bindings/fpga/xlnx,alveo-partition.yaml > new file mode 100644 > index 000000000000..ee50cb51d08e > --- /dev/null > +++ b/Documentation/devicetree/bindings/fpga/xlnx,alveo-partition.yaml > @@ -0,0 +1,76 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/fpga/xlnx,alveo-partition.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Xilinx Alveo platform partition bindings > + > +description: | > + Xilinx Alveo platform is a PCI device and has one or more partitions. A PCIe > + partition is programmed dynamically and contains a set of hardware > + peripherals also referred to as endpoints which appear on the PCI BARs. > + This binding is defined for endpoint address translation which uses the > + the following encoding: > + > + 0xIooooooo 0xoooooooo > + > + Where: > + > + I = BAR index > + oooooo oooooooo = BAR offset > + > + As a PCI device, the Alveo platform is enumerated at runtime. Thus, > + the partition node is created by Alveo device driver. The device driver > + gets the BAR base address of the PCI device and creates the 'range' > + property for address translation. > + > +allOf: > + - $ref: /schemas/simple-bus.yaml# > + > +maintainers: > + - Lizhi Hou <lizhi.hou@xilinx.com> > + > +properties: > + compatible: > + contains: > + const: xlnx,alveo-partition > + > + "#address-cells": > + const: 2 > + > + "#size-cells": > + const: 2 > + > + ranges: true > + > +patternProperties: > + "^.*@[0-9a-f]+$": > + description: hardware endpoints belong to this partition. > + type: object > + > +required: > + - compatible > + - "#address-cells" > + - "#size-cells" > + - ranges > + > +additionalProperties: false > + > +examples: > + - | > + bus { > + #address-cells = <2>; > + #size-cells = <2>; > + xrt-part-bus@0 { > + compatible = "xlnx,alveo-partition", "simple-bus"; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges = <0x0 0x0 0x0 0xe0000000 0x0 0x2000000 > + 0x20000000 0x0 0x0 0xe4200000 0x0 0x40000>; > + pr-isolate-ulp@41000 { > + compatible = "xlnx,alveo-pr-isolation"; > + reg = <0x0 0x41000 0 0x1000>; > + }; > + }; > + }; > diff --git a/Documentation/devicetree/bindings/fpga/xlnx,alveo-pr-isolation.yaml b/Documentation/devicetree/bindings/fpga/xlnx,alveo-pr-isolation.yaml > new file mode 100644 > index 000000000000..8db949093ee0 > --- /dev/null > +++ b/Documentation/devicetree/bindings/fpga/xlnx,alveo-pr-isolation.yaml > @@ -0,0 +1,40 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/fpga/xlnx,alveo-pr-isolation.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Xilinx Partial Reconfig Isolation for Alveo platforms Expand 'Partial Reconfig' to 'Partial Reconfiguration' > + > +description: | > + The Partial Reconfig ensures glitch free operation of the inputs from > + a reconfigurable partition during partial reconfiguration on Alveo > + platform. glitch free is not descriptive. maybe describe what that reg is used for. Tom > + > +maintainers: > + - Lizhi Hou <lizhi.hou@xilinx.com> > + > +properties: > + compatible: > + const: xlnx,alveo-pr-isolation > + > + reg: > + maxItems: 1 > + > +required: > + - compatible > + - reg > + > +additionalProperties: false > + > +examples: > + - | > + bus { > + #address-cells = <2>; > + #size-cells = <2>; > + > + pr-isolation-ulp@41000 { > + compatible = "xlnx,alveo-pr-isolation"; > + reg = <0 0x41000 0 0x1000>; > + }; > + };
diff --git a/Documentation/devicetree/bindings/fpga/xlnx,alveo-partition.yaml b/Documentation/devicetree/bindings/fpga/xlnx,alveo-partition.yaml new file mode 100644 index 000000000000..ee50cb51d08e --- /dev/null +++ b/Documentation/devicetree/bindings/fpga/xlnx,alveo-partition.yaml @@ -0,0 +1,76 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/fpga/xlnx,alveo-partition.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx Alveo platform partition bindings + +description: | + Xilinx Alveo platform is a PCI device and has one or more partitions. A + partition is programmed dynamically and contains a set of hardware + peripherals also referred to as endpoints which appear on the PCI BARs. + This binding is defined for endpoint address translation which uses the + the following encoding: + + 0xIooooooo 0xoooooooo + + Where: + + I = BAR index + oooooo oooooooo = BAR offset + + As a PCI device, the Alveo platform is enumerated at runtime. Thus, + the partition node is created by Alveo device driver. The device driver + gets the BAR base address of the PCI device and creates the 'range' + property for address translation. + +allOf: + - $ref: /schemas/simple-bus.yaml# + +maintainers: + - Lizhi Hou <lizhi.hou@xilinx.com> + +properties: + compatible: + contains: + const: xlnx,alveo-partition + + "#address-cells": + const: 2 + + "#size-cells": + const: 2 + + ranges: true + +patternProperties: + "^.*@[0-9a-f]+$": + description: hardware endpoints belong to this partition. + type: object + +required: + - compatible + - "#address-cells" + - "#size-cells" + - ranges + +additionalProperties: false + +examples: + - | + bus { + #address-cells = <2>; + #size-cells = <2>; + xrt-part-bus@0 { + compatible = "xlnx,alveo-partition", "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0xe0000000 0x0 0x2000000 + 0x20000000 0x0 0x0 0xe4200000 0x0 0x40000>; + pr-isolate-ulp@41000 { + compatible = "xlnx,alveo-pr-isolation"; + reg = <0x0 0x41000 0 0x1000>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/fpga/xlnx,alveo-pr-isolation.yaml b/Documentation/devicetree/bindings/fpga/xlnx,alveo-pr-isolation.yaml new file mode 100644 index 000000000000..8db949093ee0 --- /dev/null +++ b/Documentation/devicetree/bindings/fpga/xlnx,alveo-pr-isolation.yaml @@ -0,0 +1,40 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/fpga/xlnx,alveo-pr-isolation.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx Partial Reconfig Isolation for Alveo platforms + +description: | + The Partial Reconfig ensures glitch free operation of the inputs from + a reconfigurable partition during partial reconfiguration on Alveo + platform. + +maintainers: + - Lizhi Hou <lizhi.hou@xilinx.com> + +properties: + compatible: + const: xlnx,alveo-pr-isolation + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + bus { + #address-cells = <2>; + #size-cells = <2>; + + pr-isolation-ulp@41000 { + compatible = "xlnx,alveo-pr-isolation"; + reg = <0 0x41000 0 0x1000>; + }; + };