| Message ID | 20220110015018.26359-2-kabel@kernel.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | PCI: aardvark controller fixes BATCH 4 | expand |
On Mon, Jan 10, 2022 at 02:49:56AM +0100, Marek Behún wrote: > From: Pali Rohár <pali@kernel.org> > > Header file linux/pci.h defines enum pci_interrupt_pin with corresponding > PCI_INTERRUPT_* values. > > Signed-off-by: Pali Rohár <pali@kernel.org> > Signed-off-by: Marek Behún <kabel@kernel.org> Reviewed-by: Bjorn Helgaas <bhelgaas@google.com> Thanks! > --- > drivers/pci/controller/pci-aardvark.c | 6 +----- > 1 file changed, 1 insertion(+), 5 deletions(-) > > diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c > index ec0df426863d..62baddd2ca95 100644 > --- a/drivers/pci/controller/pci-aardvark.c > +++ b/drivers/pci/controller/pci-aardvark.c > @@ -39,10 +39,6 @@ > #define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN BIT(6) > #define PCIE_CORE_ERR_CAPCTL_ECRC_CHCK BIT(7) > #define PCIE_CORE_ERR_CAPCTL_ECRC_CHCK_RCV BIT(8) > -#define PCIE_CORE_INT_A_ASSERT_ENABLE 1 > -#define PCIE_CORE_INT_B_ASSERT_ENABLE 2 > -#define PCIE_CORE_INT_C_ASSERT_ENABLE 3 > -#define PCIE_CORE_INT_D_ASSERT_ENABLE 4 > /* PIO registers base address and register offsets */ > #define PIO_BASE_ADDR 0x4000 > #define PIO_CTRL (PIO_BASE_ADDR + 0x0) > @@ -968,7 +964,7 @@ static int advk_sw_pci_bridge_init(struct advk_pcie *pcie) > bridge->conf.pref_mem_limit = cpu_to_le16(PCI_PREF_RANGE_TYPE_64); > > /* Support interrupt A for MSI feature */ > - bridge->conf.intpin = PCIE_CORE_INT_A_ASSERT_ENABLE; > + bridge->conf.intpin = PCI_INTERRUPT_INTA; > > /* Aardvark HW provides PCIe Capability structure in version 2 */ > bridge->pcie_conf.cap = cpu_to_le16(2); > -- > 2.34.1 > > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c index ec0df426863d..62baddd2ca95 100644 --- a/drivers/pci/controller/pci-aardvark.c +++ b/drivers/pci/controller/pci-aardvark.c @@ -39,10 +39,6 @@ #define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN BIT(6) #define PCIE_CORE_ERR_CAPCTL_ECRC_CHCK BIT(7) #define PCIE_CORE_ERR_CAPCTL_ECRC_CHCK_RCV BIT(8) -#define PCIE_CORE_INT_A_ASSERT_ENABLE 1 -#define PCIE_CORE_INT_B_ASSERT_ENABLE 2 -#define PCIE_CORE_INT_C_ASSERT_ENABLE 3 -#define PCIE_CORE_INT_D_ASSERT_ENABLE 4 /* PIO registers base address and register offsets */ #define PIO_BASE_ADDR 0x4000 #define PIO_CTRL (PIO_BASE_ADDR + 0x0) @@ -968,7 +964,7 @@ static int advk_sw_pci_bridge_init(struct advk_pcie *pcie) bridge->conf.pref_mem_limit = cpu_to_le16(PCI_PREF_RANGE_TYPE_64); /* Support interrupt A for MSI feature */ - bridge->conf.intpin = PCIE_CORE_INT_A_ASSERT_ENABLE; + bridge->conf.intpin = PCI_INTERRUPT_INTA; /* Aardvark HW provides PCIe Capability structure in version 2 */ bridge->pcie_conf.cap = cpu_to_le16(2);