| Message ID | 20211230123539.52786-5-anup@brainfault.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | QEMU RISC-V AIA support | expand |
Anup Patel <anup@brainfault.org> 於 2021年12月30日 週四 下午8:48寫道： > From: Anup Patel <anup.patel@wdc.com> > > The guest external interrupts from an interrupt controller are > delivered only when the Guest/VM is running (i.e. V=1). This means > any guest external interrupt which is triggered while the Guest/VM > is not running (i.e. V=0) will be missed on QEMU resulting in Guest > with sluggish response to serial console input and other I/O events. > > To solve this, we check and inject interrupt after setting V=1. > > Signed-off-by: Anup Patel <anup.patel@wdc.com> > Signed-off-by: Anup Patel <anup@brainfault.org> > Reviewed-by: Alistair Francis <alistair.francis@wdc.com> > --- > target/riscv/cpu_helper.c | 13 +++++++++++++ > 1 file changed, 13 insertions(+) > > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c > index bf50699b1f..43d6311e49 100644 > --- a/target/riscv/cpu_helper.c > +++ b/target/riscv/cpu_helper.c > @@ -325,6 +325,19 @@ void riscv_cpu_set_virt_enabled(CPURISCVState *env, > bool enable) > } > > env->virt = set_field(env->virt, VIRT_ONOFF, enable); > + > + if (enable) { > + /* > + * The guest external interrupts from an interrupt controller are > + * delivered only when the Guest/VM is running (i.e. V=1). This > means > + * any guest external interrupt which is triggered while the > Guest/VM > + * is not running (i.e. V=0) will be missed on QEMU resulting in > guest > + * with sluggish response to serial console input and other I/O > events. > + * > + * To solve this, we check and inject interrupt after setting V=1. > + */ > + riscv_cpu_update_mip(env_archcpu(env), 0, 0); > + } > } > > bool riscv_cpu_two_stage_lookup(int mmu_idx) > -- > 2.25.1 > > > Reviewed-by: Frank Chang <frank.chang@sifive.com>
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index bf50699b1f..43d6311e49 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -325,6 +325,19 @@ void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable) } env->virt = set_field(env->virt, VIRT_ONOFF, enable); + + if (enable) { + /* + * The guest external interrupts from an interrupt controller are + * delivered only when the Guest/VM is running (i.e. V=1). This means + * any guest external interrupt which is triggered while the Guest/VM + * is not running (i.e. V=0) will be missed on QEMU resulting in guest + * with sluggish response to serial console input and other I/O events. + * + * To solve this, we check and inject interrupt after setting V=1. + */ + riscv_cpu_update_mip(env_archcpu(env), 0, 0); + } } bool riscv_cpu_two_stage_lookup(int mmu_idx)