| Message ID | 20220103054706.8072-1-miles.chen@mediatek.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v4] drm/mediatek: Fix mtk_cec_mask() | expand |
Hi, Miles: Miles Chen <miles.chen@mediatek.com> 於 2022年1月3日 週一 下午1:47寫道： > > In current implementation, mtk_cec_mask() writes val into target register > and ignores the mask. After talking to our hdmi experts, mtk_cec_mask() > should read a register, clean only mask bits, and update (val | mask) bits > to the register. Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org> > > Fixes: 8f83f26891e1 ("drm/mediatek: Add HDMI support") > > Cc: Zhiqiang Lin <zhiqiang.lin@mediatek.com> > Cc: CK Hu <ck.hu@mediatek.com> > Cc: Matthias Brugger <matthias.bgg@gmail.com> > > Signed-off-by: Miles Chen <miles.chen@mediatek.com> > > --- > > Change since v1: > add Fixes tag > > Change since v2: > add explanation of mtk_cec_mask() > > Change since v3: > change misleading subject and modify the commit message since this is a bug fix patch > > --- > drivers/gpu/drm/mediatek/mtk_cec.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_cec.c b/drivers/gpu/drm/mediatek/mtk_cec.c > index e9cef5c0c8f7..cdfa648910b2 100644 > --- a/drivers/gpu/drm/mediatek/mtk_cec.c > +++ b/drivers/gpu/drm/mediatek/mtk_cec.c > @@ -85,7 +85,7 @@ static void mtk_cec_mask(struct mtk_cec *cec, unsigned int offset, > u32 tmp = readl(cec->regs + offset) & ~mask; > > tmp |= val & mask; > - writel(val, cec->regs + offset); > + writel(tmp, cec->regs + offset); > } > > void mtk_cec_set_hpd_event(struct device *dev, > -- > 2.18.0 >
Il 03/01/22 06:47, Miles Chen ha scritto: > In current implementation, mtk_cec_mask() writes val into target register > and ignores the mask. After talking to our hdmi experts, mtk_cec_mask() > should read a register, clean only mask bits, and update (val | mask) bits > to the register. > > Fixes: 8f83f26891e1 ("drm/mediatek: Add HDMI support") > > Cc: Zhiqiang Lin <zhiqiang.lin@mediatek.com> > Cc: CK Hu <ck.hu@mediatek.com> > Cc: Matthias Brugger <matthias.bgg@gmail.com> > > Signed-off-by: Miles Chen <miles.chen@mediatek.com> > Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> > --- > > Change since v1: > add Fixes tag > > Change since v2: > add explanation of mtk_cec_mask() > > Change since v3: > change misleading subject and modify the commit message since this is a bug fix patch > > --- > drivers/gpu/drm/mediatek/mtk_cec.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_cec.c b/drivers/gpu/drm/mediatek/mtk_cec.c > index e9cef5c0c8f7..cdfa648910b2 100644 > --- a/drivers/gpu/drm/mediatek/mtk_cec.c > +++ b/drivers/gpu/drm/mediatek/mtk_cec.c > @@ -85,7 +85,7 @@ static void mtk_cec_mask(struct mtk_cec *cec, unsigned int offset, > u32 tmp = readl(cec->regs + offset) & ~mask; > > tmp |= val & mask; > - writel(val, cec->regs + offset); > + writel(tmp, cec->regs + offset); > } > > void mtk_cec_set_hpd_event(struct device *dev, >
On 03/01/2022 06:47, Miles Chen wrote: > In current implementation, mtk_cec_mask() writes val into target register > and ignores the mask. After talking to our hdmi experts, mtk_cec_mask() > should read a register, clean only mask bits, and update (val | mask) bits > to the register. > > Fixes: 8f83f26891e1 ("drm/mediatek: Add HDMI support") > Normally there is no new line here. > Cc: Zhiqiang Lin <zhiqiang.lin@mediatek.com> > Cc: CK Hu <ck.hu@mediatek.com> > Cc: Matthias Brugger <matthias.bgg@gmail.com> > Neither here. > Signed-off-by: Miles Chen <miles.chen@mediatek.com> > But that are nit-picks. I leave it to the maintainer to decide if he want to fix that when applying the patch: Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Thanks a lot, Matthias > --- > > Change since v1: > add Fixes tag > > Change since v2: > add explanation of mtk_cec_mask() > > Change since v3: > change misleading subject and modify the commit message since this is a bug fix patch > > --- > drivers/gpu/drm/mediatek/mtk_cec.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_cec.c b/drivers/gpu/drm/mediatek/mtk_cec.c > index e9cef5c0c8f7..cdfa648910b2 100644 > --- a/drivers/gpu/drm/mediatek/mtk_cec.c > +++ b/drivers/gpu/drm/mediatek/mtk_cec.c > @@ -85,7 +85,7 @@ static void mtk_cec_mask(struct mtk_cec *cec, unsigned int offset, > u32 tmp = readl(cec->regs + offset) & ~mask; > > tmp |= val & mask; > - writel(val, cec->regs + offset); > + writel(tmp, cec->regs + offset); > } > > void mtk_cec_set_hpd_event(struct device *dev, >
diff --git a/drivers/gpu/drm/mediatek/mtk_cec.c b/drivers/gpu/drm/mediatek/mtk_cec.c index e9cef5c0c8f7..cdfa648910b2 100644 --- a/drivers/gpu/drm/mediatek/mtk_cec.c +++ b/drivers/gpu/drm/mediatek/mtk_cec.c @@ -85,7 +85,7 @@ static void mtk_cec_mask(struct mtk_cec *cec, unsigned int offset, u32 tmp = readl(cec->regs + offset) & ~mask; tmp |= val & mask; - writel(val, cec->regs + offset); + writel(tmp, cec->regs + offset); } void mtk_cec_set_hpd_event(struct device *dev,
In current implementation, mtk_cec_mask() writes val into target register and ignores the mask. After talking to our hdmi experts, mtk_cec_mask() should read a register, clean only mask bits, and update (val | mask) bits to the register. Fixes: 8f83f26891e1 ("drm/mediatek: Add HDMI support") Cc: Zhiqiang Lin <zhiqiang.lin@mediatek.com> Cc: CK Hu <ck.hu@mediatek.com> Cc: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Miles Chen <miles.chen@mediatek.com> --- Change since v1: add Fixes tag Change since v2: add explanation of mtk_cec_mask() Change since v3: change misleading subject and modify the commit message since this is a bug fix patch --- drivers/gpu/drm/mediatek/mtk_cec.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)