| Message ID | 20220118014522.13613-1-frank.chang@sifive.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | Add RISC-V RVV Zve32f and Zve64f extensions | expand |
On Tue, Jan 18, 2022 at 11:50 AM <frank.chang@sifive.com> wrote: > > From: Frank Chang <frank.chang@sifive.com> > > In RVV v1.0 spec, several Zve* vector extensions for embedded processors > are defined in Chapter 18.2: > https://github.com/riscv/riscv-v-spec/blob/v1.0/v-spec.adoc#zve-vector-extensions-for-embedded-processors > > This patchset implements Zve32f and Zve64f extensions. > > The port is available at: > https://github.com/sifive/qemu/tree/rvv-zve32f-zve64f-upstream-v2 > > Zve32f can be enabled with -cpu option: Zve32f=true and > Zve64f can be enabled with -cpu option: Zve64f=true. > V is not required to be enabled explicitly. > > Here's the inclusion diagram for the six standard vector extensions > quoted from Nick Knight <nick.knight@sifive.com>: > > V > | > Zve64d > | > Zve64f > / \ > Zve64x Zve32f > \ / > Zve32x > > Changelog: > > v2: > * Replace hardcoded TARGET_RISCV32 macro with get_xl(). > > Frank Chang (17): > target/riscv: rvv-1.0: Add Zve64f extension into RISC-V > target/riscv: rvv-1.0: Add Zve64f support for configuration insns > target/riscv: rvv-1.0: Add Zve64f support for load and store insns > target/riscv: rvv-1.0: Add Zve64f support for vmulh variant insns > target/riscv: rvv-1.0: Add Zve64f support for vsmul.vv and vsmul.vx > insns > target/riscv: rvv-1.0: Add Zve64f support for scalar fp insns > target/riscv: rvv-1.0: Add Zve64f support for single-width fp > reduction insns > target/riscv: rvv-1.0: Add Zve64f support for widening type-convert > insns > target/riscv: rvv-1.0: Add Zve64f support for narrowing type-convert > insns > target/riscv: rvv-1.0: Allow Zve64f extension to be turned on > target/riscv: rvv-1.0: Add Zve32f extension into RISC-V > target/riscv: rvv-1.0: Add Zve32f support for configuration insns > target/riscv: rvv-1.0: Add Zve32f support for scalar fp insns > target/riscv: rvv-1.0: Add Zve32f support for single-width fp > reduction insns > target/riscv: rvv-1.0: Add Zve32f support for widening type-convert > insns > target/riscv: rvv-1.0: Add Zve32f support for narrowing type-convert > insns > target/riscv: rvv-1.0: Allow Zve32f extension to be turned on Thanks! Applied to riscv-to-apply.next Alistair > > target/riscv/cpu.c | 6 + > target/riscv/cpu.h | 2 + > target/riscv/cpu_helper.c | 5 +- > target/riscv/csr.c | 6 +- > target/riscv/insn_trans/trans_rvv.c.inc | 219 ++++++++++++++++++++---- > target/riscv/translate.c | 4 + > 6 files changed, 205 insertions(+), 37 deletions(-) > > -- > 2.31.1 > >
From: Frank Chang <frank.chang@sifive.com> In RVV v1.0 spec, several Zve* vector extensions for embedded processors are defined in Chapter 18.2: https://github.com/riscv/riscv-v-spec/blob/v1.0/v-spec.adoc#zve-vector-extensions-for-embedded-processors This patchset implements Zve32f and Zve64f extensions. The port is available at: https://github.com/sifive/qemu/tree/rvv-zve32f-zve64f-upstream-v2 Zve32f can be enabled with -cpu option: Zve32f=true and Zve64f can be enabled with -cpu option: Zve64f=true. V is not required to be enabled explicitly. Here's the inclusion diagram for the six standard vector extensions quoted from Nick Knight <nick.knight@sifive.com>: V | Zve64d | Zve64f / \ Zve64x Zve32f \ / Zve32x Changelog: v2: * Replace hardcoded TARGET_RISCV32 macro with get_xl(). Frank Chang (17): target/riscv: rvv-1.0: Add Zve64f extension into RISC-V target/riscv: rvv-1.0: Add Zve64f support for configuration insns target/riscv: rvv-1.0: Add Zve64f support for load and store insns target/riscv: rvv-1.0: Add Zve64f support for vmulh variant insns target/riscv: rvv-1.0: Add Zve64f support for vsmul.vv and vsmul.vx insns target/riscv: rvv-1.0: Add Zve64f support for scalar fp insns target/riscv: rvv-1.0: Add Zve64f support for single-width fp reduction insns target/riscv: rvv-1.0: Add Zve64f support for widening type-convert insns target/riscv: rvv-1.0: Add Zve64f support for narrowing type-convert insns target/riscv: rvv-1.0: Allow Zve64f extension to be turned on target/riscv: rvv-1.0: Add Zve32f extension into RISC-V target/riscv: rvv-1.0: Add Zve32f support for configuration insns target/riscv: rvv-1.0: Add Zve32f support for scalar fp insns target/riscv: rvv-1.0: Add Zve32f support for single-width fp reduction insns target/riscv: rvv-1.0: Add Zve32f support for widening type-convert insns target/riscv: rvv-1.0: Add Zve32f support for narrowing type-convert insns target/riscv: rvv-1.0: Allow Zve32f extension to be turned on target/riscv/cpu.c | 6 + target/riscv/cpu.h | 2 + target/riscv/cpu_helper.c | 5 +- target/riscv/csr.c | 6 +- target/riscv/insn_trans/trans_rvv.c.inc | 219 ++++++++++++++++++++---- target/riscv/translate.c | 4 + 6 files changed, 205 insertions(+), 37 deletions(-) -- 2.31.1