| Message ID | 20220103074731.3651-2-avolmat@me.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Introduction of PCIe support on STi platform | expand |
On Mon, Jan 03, 2022 at 08:47:27AM +0100, Alain Volmat wrote: > Addition of the bindings for the Designware based PCIe controller > that can be found on STi platforms such as STiH407, STiH410 or STiH418. > > Signed-off-by: Alain Volmat <avolmat@me.com> > --- > .../devicetree/bindings/pci/snps,dw-pcie.yaml | 2 +- > .../devicetree/bindings/pci/st,st-pcie.yaml | 112 ++++++++++++++++++ > 2 files changed, 113 insertions(+), 1 deletion(-) > create mode 100644 Documentation/devicetree/bindings/pci/st,st-pcie.yaml > > diff --git a/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml b/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml > index 9ed0dfba7f89..3a92078128f7 100644 > --- a/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml > +++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml > @@ -35,7 +35,7 @@ properties: > maxItems: 5 > items: > enum: [ dbi, dbi2, config, atu, app, elbi, mgmt, ctrl, parf, cfg, link, > - ulreg, smu, mpu, apb, phy ] > + ulreg, smu, mpu, apb, phy, mem-window ] > > num-lanes: > description: | > diff --git a/Documentation/devicetree/bindings/pci/st,st-pcie.yaml b/Documentation/devicetree/bindings/pci/st,st-pcie.yaml > new file mode 100644 > index 000000000000..2fa686d573c3 > --- /dev/null > +++ b/Documentation/devicetree/bindings/pci/st,st-pcie.yaml > @@ -0,0 +1,112 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/pci/st,st-pcie.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: PCIe RC controller on ST STi platform > + > +maintainers: > + - Alain Volmat <avolmat@me.com> > + > +allOf: > + - $ref: /schemas/pci/snps,dw-pcie.yaml# > + > +properties: > + compatible: > + const: st,stih407-pcie > + > + reg: > + items: > + - description: Controller control and status registers. > + - description: PCIe configuration registers. > + - description: Memory made available to the controller > + > + reg-names: > + items: > + - const: dbi > + - const: config > + - const: mem-window I guess "mem-window" is the range for inbound DMA? Other controllers should have similar ranges. Can we use the same DT reg names used by other controllers instead of adding something new and STi-specific? > + interrupts: > + maxItems: 1 > + > + resets: > + items: > + - description: Controller reset > + - description: Powerdown reset (optional) > + minItems: 1 > + > + reset-names: > + items: > + - const: softreset > + - const: powerdown "softreset" and "powerdown" appear only in this binding. Are they really unique to STi, or can we use the same names used for other controllers?
diff --git a/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml b/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml index 9ed0dfba7f89..3a92078128f7 100644 --- a/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml @@ -35,7 +35,7 @@ properties: maxItems: 5 items: enum: [ dbi, dbi2, config, atu, app, elbi, mgmt, ctrl, parf, cfg, link, - ulreg, smu, mpu, apb, phy ] + ulreg, smu, mpu, apb, phy, mem-window ] num-lanes: description: | diff --git a/Documentation/devicetree/bindings/pci/st,st-pcie.yaml b/Documentation/devicetree/bindings/pci/st,st-pcie.yaml new file mode 100644 index 000000000000..2fa686d573c3 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/st,st-pcie.yaml @@ -0,0 +1,112 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/st,st-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: PCIe RC controller on ST STi platform + +maintainers: + - Alain Volmat <avolmat@me.com> + +allOf: + - $ref: /schemas/pci/snps,dw-pcie.yaml# + +properties: + compatible: + const: st,stih407-pcie + + reg: + items: + - description: Controller control and status registers. + - description: PCIe configuration registers. + - description: Memory made available to the controller + + reg-names: + items: + - const: dbi + - const: config + - const: mem-window + + interrupts: + maxItems: 1 + + resets: + items: + - description: Controller reset + - description: Powerdown reset (optional) + minItems: 1 + + reset-names: + items: + - const: softreset + - const: powerdown + minItems: 1 + + phys: + maxItems: 1 + + phy-names: + const: pcie + + reset-gpios: true + + st,syscfg: + $ref: "/schemas/types.yaml#/definitions/phandle-array" + description: syscfg node phandle and offsets of the 2 registers + controlling root complex and ltssm. + +required: + - interrupts + - '#interrupt-cells' + - interrupt-map + - interrupt-map-mask + - resets + - reset-names + - phys + - phy-names + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/phy/phy.h> + #include <dt-bindings/reset/stih407-resets.h> + pcie1: pcie@9b10000 { + compatible = "st,stih407-pcie"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + reg = <0x09b10000 0x1000>, + <0x3fff0000 0x10000>, + <0x40000000 0xc0000000>; + reg-names = "dbi", "config", "mem-window"; + + #interrupt-cells = <1>; + interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "msi"; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &intc GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; + + st,syscfg = <&syscfg_core 0xdc 0xe4>; + + ranges = <0x82000000 0 0x30000000 0x30000000 0 0x05550000>, /* non-prefetchable memory */ + <0xc2000000 0 0x35550000 0x35550000 0 0x0AAA0000>; /* prefetchable memory */ + bus-range = <0x00 0xff>; + + resets = <&softreset STIH407_PCIE1_SOFTRESET>, + <&powerdown STIH407_PCIE1_POWERDOWN>; + + reset-names = "softreset", "powerdown"; + + phys = <&phy_port1 PHY_TYPE_PCIE>; + phy-names = "pcie"; + + reset-gpios = <&pio34 5 GPIO_ACTIVE_LOW>; + };
Addition of the bindings for the Designware based PCIe controller that can be found on STi platforms such as STiH407, STiH410 or STiH418. Signed-off-by: Alain Volmat <avolmat@me.com> --- .../devicetree/bindings/pci/snps,dw-pcie.yaml | 2 +- .../devicetree/bindings/pci/st,st-pcie.yaml | 112 ++++++++++++++++++ 2 files changed, 113 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/pci/st,st-pcie.yaml