Message ID | 1638432158-4119-5-git-send-email-hongxing.zhu@nxp.com (mailing list archive) |
---|---|
State | Not Applicable |
Delegated to: | Lorenzo Pieralisi |
Headers | show |
Series | Add the imx8m pcie phy driver and imx8mm pcie support | expand |
On Thu, Dec 02, 2021 at 04:02:34PM +0800, Richard Zhu wrote: > Add the PCIe PHY support on iMX8MM platforms. > > Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> > Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> > Reviewed-by: Tim Harvey <tharvey@gateworks.com> > Tested-by: Tim Harvey <tharvey@gateworks.com> Applied, thanks!
diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index c2f3f118f82e..0844f3144887 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -1135,6 +1135,19 @@ usbmisc2: usbmisc@32e50200 { reg = <0x32e50200 0x200>; }; + pcie_phy: pcie-phy@32f00000 { + compatible = "fsl,imx8mm-pcie-phy"; + reg = <0x32f00000 0x10000>; + clocks = <&clk IMX8MM_CLK_PCIE1_PHY>; + clock-names = "ref"; + assigned-clocks = <&clk IMX8MM_CLK_PCIE1_PHY>; + assigned-clock-rates = <100000000>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_100M>; + resets = <&src IMX8MQ_RESET_PCIEPHY>; + reset-names = "pciephy"; + #phy-cells = <0>; + status = "disabled"; + }; }; dma_apbh: dma-controller@33000000 {