| Message ID | 20220107101425.6917-10-jason-jh.lin@mediatek.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add Mediatek Soc DRM (vdosys0) support for mt8195 | expand |
Hi, Jason: On Fri, 2022-01-07 at 18:14 +0800, jason-jh.lin wrote: > Add mtk-mutex support for mt8195 vdosys0. > > Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com> > Acked-by: AngeloGioacchino Del Regno < > angelogioacchino.delregno@collabora.com> > --- > This patch is base on [1] > [1] Add mmsys and mutex support for MDP > - > https://patchwork.kernel.org/project/linux-mediatek/cover/20220104091712.25670-1-moudy.ho@mediatek.com/ > --- > drivers/soc/mediatek/mtk-mutex.c | 95 > +++++++++++++++++++++++++++++++- > 1 file changed, 92 insertions(+), 3 deletions(-) > > diff --git a/drivers/soc/mediatek/mtk-mutex.c > b/drivers/soc/mediatek/mtk-mutex.c > index 615c42260a50..89daab7e6863 100644 > --- a/drivers/soc/mediatek/mtk-mutex.c > +++ b/drivers/soc/mediatek/mtk-mutex.c > @@ -21,6 +21,9 @@ > #define MT8183_MUTEX0_MOD0 0x30 > #define MT8183_MUTEX0_SOF0 0x2c > > +#define MT8195_DISP_MUTEX0_MOD0 0x30 > +#define MT8195_DISP_MUTEX0_SOF 0x2c > + > #define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n)) > #define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n)) > #define DISP_REG_MUTEX_RST(n) (0x28 + 0x20 * > (n)) > @@ -83,6 +86,36 @@ > #define MT8173_MUTEX_MOD_DISP_PWM1 24 > #define MT8173_MUTEX_MOD_DISP_OD 25 > > +#define MT8195_MUTEX_MOD_DISP_OVL0 0 > +#define MT8195_MUTEX_MOD_DISP_WDMA0 1 > +#define MT8195_MUTEX_MOD_DISP_RDMA0 2 > +#define MT8195_MUTEX_MOD_DISP_COLOR0 3 > +#define MT8195_MUTEX_MOD_DISP_CCORR0 4 > +#define MT8195_MUTEX_MOD_DISP_AAL0 5 > +#define MT8195_MUTEX_MOD_DISP_GAMMA0 6 > +#define MT8195_MUTEX_MOD_DISP_DITHER0 7 > +#define MT8195_MUTEX_MOD_DISP_DSI0 8 > +#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0 9 > +#define MT8195_MUTEX_MOD_DISP_OVL1 10 > +#define MT8195_MUTEX_MOD_DISP_WDMA1 11 > +#define MT8195_MUTEX_MOD_DISP_RDMA1 12 > +#define MT8195_MUTEX_MOD_DISP_COLOR1 13 > +#define MT8195_MUTEX_MOD_DISP_CCORR1 14 > +#define MT8195_MUTEX_MOD_DISP_AAL1 15 > +#define MT8195_MUTEX_MOD_DISP_GAMMA1 16 > +#define MT8195_MUTEX_MOD_DISP_DITHER1 17 > +#define MT8195_MUTEX_MOD_DISP_DSI1 18 > +#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE1 19 > +#define MT8195_MUTEX_MOD_DISP_VPP_MERGE 20 > +#define MT8195_MUTEX_MOD_DISP_DP_INTF0 21 > +#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY0 22 > +#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY1 23 > +#define MT8195_MUTEX_MOD_DISP_VDO1_DL_RELAY2 24 > +#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY3 25 > +#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY4 26 > +#define MT8195_MUTEX_MOD_DISP_PWM0 27 > +#define MT8195_MUTEX_MOD_DISP_PWM1 28 > + > #define MT2712_MUTEX_MOD_DISP_PWM2 10 > #define MT2712_MUTEX_MOD_DISP_OVL0 11 > #define MT2712_MUTEX_MOD_DISP_OVL1 12 > @@ -119,9 +152,21 @@ > #define MT8167_MUTEX_SOF_DPI1 3 > #define MT8183_MUTEX_SOF_DSI0 1 > #define MT8183_MUTEX_SOF_DPI0 2 > +#define MT8195_MUTEX_SOF_DSI0 1 > +#define MT8195_MUTEX_SOF_DSI1 2 > +#define MT8195_MUTEX_SOF_DP_INTF0 3 > +#define MT8195_MUTEX_SOF_DP_INTF1 4 > +#define MT8195_MUTEX_SOF_DPI0 6 /* for > HDMI_TX */ > +#define MT8195_MUTEX_SOF_DPI1 5 /* for > digital video out */ > > #define MT8183_MUTEX_EOF_DSI0 (MT8183_MUTEX_S > OF_DSI0 << 6) > #define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_S > OF_DPI0 << 6) > +#define MT8195_MUTEX_EOF_DSI0 (MT8195_MUTEX_S > OF_DSI0 << 7) > +#define MT8195_MUTEX_EOF_DSI1 (MT8195_MUTEX_S > OF_DSI1 << 7) > +#define MT8195_MUTEX_EOF_DP_INTF0 (MT8195_MUTEX_SOF_DP_IN > TF0 << 7) > +#define MT8195_MUTEX_EOF_DP_INTF1 (MT8195_MUTEX_SOF_DP_IN > TF1 << 7) > +#define MT8195_MUTEX_EOF_DPI0 (MT8195_MUTEX_S > OF_DPI0 << 7) > +#define MT8195_MUTEX_EOF_DPI1 (MT8195_MUTEX_S > OF_DPI1 << 7) > > #define MT8183_MUTEX_MDP_START 5 > #define MT8183_MUTEX_MDP_MOD_MASK 0x07FFFFFF > @@ -148,6 +193,9 @@ enum mtk_mutex_sof_id { > MUTEX_SOF_DPI1, > MUTEX_SOF_DSI2, > MUTEX_SOF_DSI3, > + MUTEX_SOF_DP_INTF0, > + MUTEX_SOF_DP_INTF1, > + DDP_MUTEX_SOF_MAX, > }; > > struct mtk_mutex_data { > @@ -274,7 +322,23 @@ static const unsigned int > mt8192_mutex_mod[DDP_COMPONENT_ID_MAX] = { > [DDP_COMPONENT_RDMA4] = MT8192_MUTEX_MOD_DISP_RDMA4, > }; > > -static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = { > +static const unsigned int mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = { > + [DDP_COMPONENT_OVL0] = MT8195_MUTEX_MOD_DISP_OVL0, > + [DDP_COMPONENT_WDMA0] = MT8195_MUTEX_MOD_DISP_WDMA0, > + [DDP_COMPONENT_RDMA0] = MT8195_MUTEX_MOD_DISP_RDMA0, > + [DDP_COMPONENT_COLOR0] = MT8195_MUTEX_MOD_DISP_COLOR0, > + [DDP_COMPONENT_CCORR] = MT8195_MUTEX_MOD_DISP_CCORR0, > + [DDP_COMPONENT_AAL0] = MT8195_MUTEX_MOD_DISP_AAL0, > + [DDP_COMPONENT_GAMMA] = MT8195_MUTEX_MOD_DISP_GAMMA0, > + [DDP_COMPONENT_DITHER] = MT8195_MUTEX_MOD_DISP_DITHER0, > + [DDP_COMPONENT_MERGE0] = MT8195_MUTEX_MOD_DISP_VPP_MERGE, > + [DDP_COMPONENT_DSC0] = MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0, > + [DDP_COMPONENT_DSI0] = MT8195_MUTEX_MOD_DISP_DSI0, > + [DDP_COMPONENT_PWM0] = MT8195_MUTEX_MOD_DISP_PWM0, > + [DDP_COMPONENT_DP_INTF0] = MT8195_MUTEX_MOD_DISP_DP_INTF0, > +}; > + > +static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_MAX] = { > [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, > [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0, > [MUTEX_SOF_DSI1] = MUTEX_SOF_DSI1, > @@ -284,7 +348,7 @@ static const unsigned int > mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = { > [MUTEX_SOF_DSI3] = MUTEX_SOF_DSI3, > }; > > -static const unsigned int mt8167_mutex_sof[MUTEX_SOF_DSI3 + 1] = { > +static const unsigned int mt8167_mutex_sof[DDP_MUTEX_SOF_MAX] = { > [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, > [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0, > [MUTEX_SOF_DPI0] = MT8167_MUTEX_SOF_DPI0, > @@ -292,7 +356,7 @@ static const unsigned int > mt8167_mutex_sof[MUTEX_SOF_DSI3 + 1] = { > }; > > /* Add EOF setting so overlay hardware can receive frame done irq */ > -static const unsigned int mt8183_mutex_sof[MUTEX_SOF_DSI3 + 1] = { > +static const unsigned int mt8183_mutex_sof[DDP_MUTEX_SOF_MAX] = { > [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, > [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0, > [MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | > MT8183_MUTEX_EOF_DPI0, > @@ -306,6 +370,18 @@ static const unsigned int > mt8183_mutex_mdp_offset[MDP_PIPE_MAX] = { > [MDP_PIPE_WPEI2] = MT8183_MUTEX_MDP_START + 3 > }; > > +static const unsigned int mt8195_mutex_sof[DDP_MUTEX_SOF_MAX] = { > + [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, > + [MUTEX_SOF_DSI0] = MT8195_MUTEX_SOF_DSI0 | > MT8195_MUTEX_EOF_DSI0, > + [MUTEX_SOF_DSI1] = MT8195_MUTEX_SOF_DSI1 | > MT8195_MUTEX_EOF_DSI1, > + [MUTEX_SOF_DPI0] = MT8195_MUTEX_SOF_DPI0 | > MT8195_MUTEX_EOF_DPI0, > + [MUTEX_SOF_DPI1] = MT8195_MUTEX_SOF_DPI1 | > MT8195_MUTEX_EOF_DPI1, > + [MUTEX_SOF_DP_INTF0] = > + MT8195_MUTEX_SOF_DP_INTF0 | MT8195_MUTEX_EOF_DP_INTF0, Why add EOF? Add comment for this. Regards, CK > + [MUTEX_SOF_DP_INTF1] = > + MT8195_MUTEX_SOF_DP_INTF1 | MT8195_MUTEX_EOF_DP_INTF1, > +}; > + > static const struct mtk_mutex_data mt2701_mutex_driver_data = { > .mutex_mod = mt2701_mutex_mod, > .mutex_sof = mt2712_mutex_sof, > @@ -355,6 +431,13 @@ static const struct mtk_mutex_data > mt8192_mutex_driver_data = { > .mutex_sof_reg = MT8183_MUTEX0_SOF0, > }; > > +static const struct mtk_mutex_data mt8195_mutex_driver_data = { > + .mutex_mod = mt8195_mutex_mod, > + .mutex_sof = mt8195_mutex_sof, > + .mutex_mod_reg = MT8195_DISP_MUTEX0_MOD0, > + .mutex_sof_reg = MT8195_DISP_MUTEX0_SOF, > +}; > + > struct mtk_mutex *mtk_mutex_get(struct device *dev) > { > struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev); > @@ -442,6 +525,9 @@ void mtk_mutex_add_comp(struct mtk_mutex *mutex, > case DDP_COMPONENT_DPI1: > sof_id = MUTEX_SOF_DPI1; > break; > + case DDP_COMPONENT_DP_INTF0: > + sof_id = MUTEX_SOF_DP_INTF0; > + break; > default: > if (mtx->data->mutex_mod[id] < 32) { > offset = DISP_REG_MUTEX_MOD(mtx->data- > >mutex_mod_reg, > @@ -481,6 +567,7 @@ void mtk_mutex_remove_comp(struct mtk_mutex > *mutex, > case DDP_COMPONENT_DSI3: > case DDP_COMPONENT_DPI0: > case DDP_COMPONENT_DPI1: > + case DDP_COMPONENT_DP_INTF0: > writel_relaxed(MUTEX_SOF_SINGLE_MODE, > mtx->regs + > DISP_REG_MUTEX_SOF(mtx->data- > >mutex_sof_reg, > @@ -678,6 +765,8 @@ static const struct of_device_id > mutex_driver_dt_match[] = { > .data = &mt8183_mutex_driver_data}, > { .compatible = "mediatek,mt8192-disp-mutex", > .data = &mt8192_mutex_driver_data}, > + { .compatible = "mediatek,mt8195-disp-mutex", > + .data = &mt8195_mutex_driver_data}, > {}, > }; > MODULE_DEVICE_TABLE(of, mutex_driver_dt_match);
Hi CK, Thanks for the reviews. On Mon, 2022-01-24 at 17:13 +0800, CK Hu wrote: > Hi, Jason: > > On Fri, 2022-01-07 at 18:14 +0800, jason-jh.lin wrote: > > Add mtk-mutex support for mt8195 vdosys0. > > > > Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com> > > Acked-by: AngeloGioacchino Del Regno < > > angelogioacchino.delregno@collabora.com> > > --- > > This patch is base on [1] > > [1] Add mmsys and mutex support for MDP > > - > > https://patchwork.kernel.org/project/linux-mediatek/cover/20220104091712.25670-1-moudy.ho@mediatek.com/ > > --- > > drivers/soc/mediatek/mtk-mutex.c | 95 > > +++++++++++++++++++++++++++++++- > > 1 file changed, 92 insertions(+), 3 deletions(-) > > > > diff --git a/drivers/soc/mediatek/mtk-mutex.c > > b/drivers/soc/mediatek/mtk-mutex.c > > index 615c42260a50..89daab7e6863 100644 > > --- a/drivers/soc/mediatek/mtk-mutex.c > > +++ b/drivers/soc/mediatek/mtk-mutex.c > > @@ -21,6 +21,9 @@ > > #define MT8183_MUTEX0_MOD0 0x30 > > #define MT8183_MUTEX0_SOF0 0x2c [snip] > > > > +static const unsigned int mt8195_mutex_sof[DDP_MUTEX_SOF_MAX] = { > > + [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, > > + [MUTEX_SOF_DSI0] = MT8195_MUTEX_SOF_DSI0 | > > MT8195_MUTEX_EOF_DSI0, > > + [MUTEX_SOF_DSI1] = MT8195_MUTEX_SOF_DSI1 | > > MT8195_MUTEX_EOF_DSI1, > > + [MUTEX_SOF_DPI0] = MT8195_MUTEX_SOF_DPI0 | > > MT8195_MUTEX_EOF_DPI0, > > + [MUTEX_SOF_DPI1] = MT8195_MUTEX_SOF_DPI1 | > > MT8195_MUTEX_EOF_DPI1, > > + [MUTEX_SOF_DP_INTF0] = > > + MT8195_MUTEX_SOF_DP_INTF0 | MT8195_MUTEX_EOF_DP_INTF0, > > Why add EOF? Add comment for this. > > Regards, > CK > OK, I' ll add this comment: /* * To support refresh mode(video mode), DISP_REG_MUTEX_SOF should * select the EOF source and configure the EOF plus timing from the * module that provides the timing signal. * So that MUTEX can not only send a STREAM_DONE event to GCE * but also detect the error at end of frame(EAEOF) when EOF signal * arrives. */ Regards, Jason-JH.Lin > > + [MUTEX_SOF_DP_INTF1] = > > + MT8195_MUTEX_SOF_DP_INTF1 | MT8195_MUTEX_EOF_DP_INTF1, > > +}; > > + > > static const struct mtk_mutex_data mt2701_mutex_driver_data = { > > .mutex_mod = mt2701_mutex_mod, > > .mutex_sof = mt2712_mutex_sof, > > @@ -355,6 +431,13 @@ static const struct mtk_mutex_data > > mt8192_mutex_driver_data = { > > .mutex_sof_reg = MT8183_MUTEX0_SOF0, > > }; > > > > +static const struct mtk_mutex_data mt8195_mutex_driver_data = { > > + .mutex_mod = mt8195_mutex_mod, > > + .mutex_sof = mt8195_mutex_sof, > > + .mutex_mod_reg = MT8195_DISP_MUTEX0_MOD0, > > + .mutex_sof_reg = MT8195_DISP_MUTEX0_SOF, > > +}; > > + > > struct mtk_mutex *mtk_mutex_get(struct device *dev) > > { > > struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev); > > @@ -442,6 +525,9 @@ void mtk_mutex_add_comp(struct mtk_mutex > > *mutex, > > case DDP_COMPONENT_DPI1: > > sof_id = MUTEX_SOF_DPI1; > > break; > > + case DDP_COMPONENT_DP_INTF0: > > + sof_id = MUTEX_SOF_DP_INTF0; > > + break; > > default: > > if (mtx->data->mutex_mod[id] < 32) { > > offset = DISP_REG_MUTEX_MOD(mtx->data- > > > mutex_mod_reg, > > > > @@ -481,6 +567,7 @@ void mtk_mutex_remove_comp(struct mtk_mutex > > *mutex, > > case DDP_COMPONENT_DSI3: > > case DDP_COMPONENT_DPI0: > > case DDP_COMPONENT_DPI1: > > + case DDP_COMPONENT_DP_INTF0: > > writel_relaxed(MUTEX_SOF_SINGLE_MODE, > > mtx->regs + > > DISP_REG_MUTEX_SOF(mtx->data- > > > mutex_sof_reg, > > > > @@ -678,6 +765,8 @@ static const struct of_device_id > > mutex_driver_dt_match[] = { > > .data = &mt8183_mutex_driver_data}, > > { .compatible = "mediatek,mt8192-disp-mutex", > > .data = &mt8192_mutex_driver_data}, > > + { .compatible = "mediatek,mt8195-disp-mutex", > > + .data = &mt8195_mutex_driver_data}, > > {}, > > }; > > MODULE_DEVICE_TABLE(of, mutex_driver_dt_match); > >
diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c index 615c42260a50..89daab7e6863 100644 --- a/drivers/soc/mediatek/mtk-mutex.c +++ b/drivers/soc/mediatek/mtk-mutex.c @@ -21,6 +21,9 @@ #define MT8183_MUTEX0_MOD0 0x30 #define MT8183_MUTEX0_SOF0 0x2c +#define MT8195_DISP_MUTEX0_MOD0 0x30 +#define MT8195_DISP_MUTEX0_SOF 0x2c + #define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n)) #define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n)) #define DISP_REG_MUTEX_RST(n) (0x28 + 0x20 * (n)) @@ -83,6 +86,36 @@ #define MT8173_MUTEX_MOD_DISP_PWM1 24 #define MT8173_MUTEX_MOD_DISP_OD 25 +#define MT8195_MUTEX_MOD_DISP_OVL0 0 +#define MT8195_MUTEX_MOD_DISP_WDMA0 1 +#define MT8195_MUTEX_MOD_DISP_RDMA0 2 +#define MT8195_MUTEX_MOD_DISP_COLOR0 3 +#define MT8195_MUTEX_MOD_DISP_CCORR0 4 +#define MT8195_MUTEX_MOD_DISP_AAL0 5 +#define MT8195_MUTEX_MOD_DISP_GAMMA0 6 +#define MT8195_MUTEX_MOD_DISP_DITHER0 7 +#define MT8195_MUTEX_MOD_DISP_DSI0 8 +#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0 9 +#define MT8195_MUTEX_MOD_DISP_OVL1 10 +#define MT8195_MUTEX_MOD_DISP_WDMA1 11 +#define MT8195_MUTEX_MOD_DISP_RDMA1 12 +#define MT8195_MUTEX_MOD_DISP_COLOR1 13 +#define MT8195_MUTEX_MOD_DISP_CCORR1 14 +#define MT8195_MUTEX_MOD_DISP_AAL1 15 +#define MT8195_MUTEX_MOD_DISP_GAMMA1 16 +#define MT8195_MUTEX_MOD_DISP_DITHER1 17 +#define MT8195_MUTEX_MOD_DISP_DSI1 18 +#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE1 19 +#define MT8195_MUTEX_MOD_DISP_VPP_MERGE 20 +#define MT8195_MUTEX_MOD_DISP_DP_INTF0 21 +#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY0 22 +#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY1 23 +#define MT8195_MUTEX_MOD_DISP_VDO1_DL_RELAY2 24 +#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY3 25 +#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY4 26 +#define MT8195_MUTEX_MOD_DISP_PWM0 27 +#define MT8195_MUTEX_MOD_DISP_PWM1 28 + #define MT2712_MUTEX_MOD_DISP_PWM2 10 #define MT2712_MUTEX_MOD_DISP_OVL0 11 #define MT2712_MUTEX_MOD_DISP_OVL1 12 @@ -119,9 +152,21 @@ #define MT8167_MUTEX_SOF_DPI1 3 #define MT8183_MUTEX_SOF_DSI0 1 #define MT8183_MUTEX_SOF_DPI0 2 +#define MT8195_MUTEX_SOF_DSI0 1 +#define MT8195_MUTEX_SOF_DSI1 2 +#define MT8195_MUTEX_SOF_DP_INTF0 3 +#define MT8195_MUTEX_SOF_DP_INTF1 4 +#define MT8195_MUTEX_SOF_DPI0 6 /* for HDMI_TX */ +#define MT8195_MUTEX_SOF_DPI1 5 /* for digital video out */ #define MT8183_MUTEX_EOF_DSI0 (MT8183_MUTEX_SOF_DSI0 << 6) #define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_SOF_DPI0 << 6) +#define MT8195_MUTEX_EOF_DSI0 (MT8195_MUTEX_SOF_DSI0 << 7) +#define MT8195_MUTEX_EOF_DSI1 (MT8195_MUTEX_SOF_DSI1 << 7) +#define MT8195_MUTEX_EOF_DP_INTF0 (MT8195_MUTEX_SOF_DP_INTF0 << 7) +#define MT8195_MUTEX_EOF_DP_INTF1 (MT8195_MUTEX_SOF_DP_INTF1 << 7) +#define MT8195_MUTEX_EOF_DPI0 (MT8195_MUTEX_SOF_DPI0 << 7) +#define MT8195_MUTEX_EOF_DPI1 (MT8195_MUTEX_SOF_DPI1 << 7) #define MT8183_MUTEX_MDP_START 5 #define MT8183_MUTEX_MDP_MOD_MASK 0x07FFFFFF @@ -148,6 +193,9 @@ enum mtk_mutex_sof_id { MUTEX_SOF_DPI1, MUTEX_SOF_DSI2, MUTEX_SOF_DSI3, + MUTEX_SOF_DP_INTF0, + MUTEX_SOF_DP_INTF1, + DDP_MUTEX_SOF_MAX, }; struct mtk_mutex_data { @@ -274,7 +322,23 @@ static const unsigned int mt8192_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_RDMA4] = MT8192_MUTEX_MOD_DISP_RDMA4, }; -static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = { +static const unsigned int mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = { + [DDP_COMPONENT_OVL0] = MT8195_MUTEX_MOD_DISP_OVL0, + [DDP_COMPONENT_WDMA0] = MT8195_MUTEX_MOD_DISP_WDMA0, + [DDP_COMPONENT_RDMA0] = MT8195_MUTEX_MOD_DISP_RDMA0, + [DDP_COMPONENT_COLOR0] = MT8195_MUTEX_MOD_DISP_COLOR0, + [DDP_COMPONENT_CCORR] = MT8195_MUTEX_MOD_DISP_CCORR0, + [DDP_COMPONENT_AAL0] = MT8195_MUTEX_MOD_DISP_AAL0, + [DDP_COMPONENT_GAMMA] = MT8195_MUTEX_MOD_DISP_GAMMA0, + [DDP_COMPONENT_DITHER] = MT8195_MUTEX_MOD_DISP_DITHER0, + [DDP_COMPONENT_MERGE0] = MT8195_MUTEX_MOD_DISP_VPP_MERGE, + [DDP_COMPONENT_DSC0] = MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0, + [DDP_COMPONENT_DSI0] = MT8195_MUTEX_MOD_DISP_DSI0, + [DDP_COMPONENT_PWM0] = MT8195_MUTEX_MOD_DISP_PWM0, + [DDP_COMPONENT_DP_INTF0] = MT8195_MUTEX_MOD_DISP_DP_INTF0, +}; + +static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_MAX] = { [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0, [MUTEX_SOF_DSI1] = MUTEX_SOF_DSI1, @@ -284,7 +348,7 @@ static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = { [MUTEX_SOF_DSI3] = MUTEX_SOF_DSI3, }; -static const unsigned int mt8167_mutex_sof[MUTEX_SOF_DSI3 + 1] = { +static const unsigned int mt8167_mutex_sof[DDP_MUTEX_SOF_MAX] = { [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0, [MUTEX_SOF_DPI0] = MT8167_MUTEX_SOF_DPI0, @@ -292,7 +356,7 @@ static const unsigned int mt8167_mutex_sof[MUTEX_SOF_DSI3 + 1] = { }; /* Add EOF setting so overlay hardware can receive frame done irq */ -static const unsigned int mt8183_mutex_sof[MUTEX_SOF_DSI3 + 1] = { +static const unsigned int mt8183_mutex_sof[DDP_MUTEX_SOF_MAX] = { [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0, [MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0, @@ -306,6 +370,18 @@ static const unsigned int mt8183_mutex_mdp_offset[MDP_PIPE_MAX] = { [MDP_PIPE_WPEI2] = MT8183_MUTEX_MDP_START + 3 }; +static const unsigned int mt8195_mutex_sof[DDP_MUTEX_SOF_MAX] = { + [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, + [MUTEX_SOF_DSI0] = MT8195_MUTEX_SOF_DSI0 | MT8195_MUTEX_EOF_DSI0, + [MUTEX_SOF_DSI1] = MT8195_MUTEX_SOF_DSI1 | MT8195_MUTEX_EOF_DSI1, + [MUTEX_SOF_DPI0] = MT8195_MUTEX_SOF_DPI0 | MT8195_MUTEX_EOF_DPI0, + [MUTEX_SOF_DPI1] = MT8195_MUTEX_SOF_DPI1 | MT8195_MUTEX_EOF_DPI1, + [MUTEX_SOF_DP_INTF0] = + MT8195_MUTEX_SOF_DP_INTF0 | MT8195_MUTEX_EOF_DP_INTF0, + [MUTEX_SOF_DP_INTF1] = + MT8195_MUTEX_SOF_DP_INTF1 | MT8195_MUTEX_EOF_DP_INTF1, +}; + static const struct mtk_mutex_data mt2701_mutex_driver_data = { .mutex_mod = mt2701_mutex_mod, .mutex_sof = mt2712_mutex_sof, @@ -355,6 +431,13 @@ static const struct mtk_mutex_data mt8192_mutex_driver_data = { .mutex_sof_reg = MT8183_MUTEX0_SOF0, }; +static const struct mtk_mutex_data mt8195_mutex_driver_data = { + .mutex_mod = mt8195_mutex_mod, + .mutex_sof = mt8195_mutex_sof, + .mutex_mod_reg = MT8195_DISP_MUTEX0_MOD0, + .mutex_sof_reg = MT8195_DISP_MUTEX0_SOF, +}; + struct mtk_mutex *mtk_mutex_get(struct device *dev) { struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev); @@ -442,6 +525,9 @@ void mtk_mutex_add_comp(struct mtk_mutex *mutex, case DDP_COMPONENT_DPI1: sof_id = MUTEX_SOF_DPI1; break; + case DDP_COMPONENT_DP_INTF0: + sof_id = MUTEX_SOF_DP_INTF0; + break; default: if (mtx->data->mutex_mod[id] < 32) { offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg, @@ -481,6 +567,7 @@ void mtk_mutex_remove_comp(struct mtk_mutex *mutex, case DDP_COMPONENT_DSI3: case DDP_COMPONENT_DPI0: case DDP_COMPONENT_DPI1: + case DDP_COMPONENT_DP_INTF0: writel_relaxed(MUTEX_SOF_SINGLE_MODE, mtx->regs + DISP_REG_MUTEX_SOF(mtx->data->mutex_sof_reg, @@ -678,6 +765,8 @@ static const struct of_device_id mutex_driver_dt_match[] = { .data = &mt8183_mutex_driver_data}, { .compatible = "mediatek,mt8192-disp-mutex", .data = &mt8192_mutex_driver_data}, + { .compatible = "mediatek,mt8195-disp-mutex", + .data = &mt8195_mutex_driver_data}, {}, }; MODULE_DEVICE_TABLE(of, mutex_driver_dt_match);