[v3,2/7] target/riscv: riscv_tr_init_disas_context: copy pointer-to-cfg into cfg_ptr

Commit Message

Philipp Tomsich Jan. 28, 2022, 2:56 p.m. UTC

As the number of extensions is growing, copying them individiually
into the DisasContext will scale less and less... instead we populate
a pointer to the RISCVCPUConfig structure in the DisasContext.

This adds an extra indirection when checking for the availability of
an extension (compared to copying the fields into DisasContext).
While not a performance problem today, we can always (shallow) copy
the entire structure into the DisasContext (instead of putting a
pointer to it) if this is ever deemed necessary.

Signed-off-by: Philipp Tomsich <[e-mail]>
Suggested-by: Richard Henderson <[e-mail]>

---

Changes in v3:
- (new patch) copy pointer to element cfg into DisasContext

 target/riscv/translate.c | 2 ++
 1 file changed, 2 insertions(+)

Comments

Richard Henderson Jan. 30, 2022, 8:53 p.m. UTC | #1

On 1/29/22 01:56, Philipp Tomsich wrote:
> As the number of extensions is growing, copying them individiually
> into the DisasContext will scale less and less... instead we populate
> a pointer to the RISCVCPUConfig structure in the DisasContext.
> 
> This adds an extra indirection when checking for the availability of
> an extension (compared to copying the fields into DisasContext).
> While not a performance problem today, we can always (shallow) copy
> the entire structure into the DisasContext (instead of putting a
> pointer to it) if this is ever deemed necessary.
> 
> Signed-off-by: Philipp Tomsich<[e-mail]>
> Suggested-by: Richard Henderson<[e-mail]>
> 
> ---
> 
> Changes in v3:
> - (new patch) copy pointer to element cfg into DisasContext
> 
>   target/riscv/translate.c | 2 ++
>   1 file changed, 2 insertions(+)

Reviewed-by: Richard Henderson <[e-mail]>

r~

Patch

diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index f0bbe80875..22d09af2df 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -76,6 +76,7 @@  typedef struct DisasContext {
     int frm;
     RISCVMXL ol;
     bool virt_enabled;
+    const struct RISCVCPUConfig *cfg_ptr;
     bool ext_ifencei;
     bool ext_zfh;
     bool ext_zfhmin;
@@ -908,6 +909,7 @@  static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
 #endif
     ctx->misa_ext = env->misa_ext;
     ctx->frm = -1;  /* unknown rounding mode */
+    ctx->cfg_ptr = &(cpu->cfg);
     ctx->ext_ifencei = cpu->cfg.ext_ifencei;
     ctx->ext_zfh = cpu->cfg.ext_zfh;
     ctx->ext_zfhmin = cpu->cfg.ext_zfhmin;