Message ID | 20220127091808.1043392-4-miquel.raynal@bootlin.com (mailing list archive) |
---|---|
State | Accepted |
Commit | a9be454927de3b6df8ca4cbd88e019e52b73d4b4 |
Headers | show |
Series | External ECC engines & Macronix support | expand |
On Thu, 2022-01-27 at 09:17:58 UTC, Miquel Raynal wrote: > This controller has DTR support, so advertize it with a capability now > that the spi-controller structure contains this new field. This will > later be used by the core to discriminate whether an operation is > supported or not, in a more generic way than having different helpers. > > Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> > Reviewed-by: Pratyush Yadav <p.yadav@ti.com> > Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> > Link: https://lore.kernel.org/linux-mtd/20220104083631.40776-4-miquel.raynal@bootlin.com Applied to https://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux.git spi-mem-ecc. Miquel
diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c index b808c94641fa..455b90d1feed 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -1595,6 +1595,10 @@ static const struct spi_controller_mem_ops cqspi_mem_ops = { .supports_op = cqspi_supports_mem_op, }; +static const struct spi_controller_mem_caps cqspi_mem_caps = { + .dtr = true, +}; + static int cqspi_setup_flash(struct cqspi_st *cqspi) { struct platform_device *pdev = cqspi->pdev; @@ -1652,6 +1656,7 @@ static int cqspi_probe(struct platform_device *pdev) } master->mode_bits = SPI_RX_QUAD | SPI_RX_DUAL; master->mem_ops = &cqspi_mem_ops; + master->mem_caps = &cqspi_mem_caps; master->dev.of_node = pdev->dev.of_node; cqspi = spi_master_get_devdata(master);