| Message ID | 164298418268.3018233.17790073375430834911.stgit@dwillia2-desk3.amr.corp.intel.com (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | d621bc2e7282f9955033a6359877fd4ac4be60e1 |
| Headers | show |
| Series | CXL.mem Topology Discovery and Hotplug Support | expand |
On Sun, 23 Jan 2022 16:29:42 -0800 Dan Williams <dan.j.williams@intel.com> wrote: > Fix a '\n' vs '/n' typo. > > Fixes: 08422378c4ad ("cxl/pci: Add HDM decoder capabilities") > Signed-off-by: Dan Williams <dan.j.williams@intel.com> FWIW Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Possibly worth pulling this out and sending separately. Jonathan > --- > drivers/cxl/core/regs.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/cxl/core/regs.c b/drivers/cxl/core/regs.c > index 0d63758e2605..12a6cbddf110 100644 > --- a/drivers/cxl/core/regs.c > +++ b/drivers/cxl/core/regs.c > @@ -50,7 +50,7 @@ void cxl_probe_component_regs(struct device *dev, void __iomem *base, > > if (FIELD_GET(CXL_CM_CAP_HDR_ID_MASK, cap_array) != CM_CAP_HDR_CAP_ID) { > dev_err(dev, > - "Couldn't locate the CXL.cache and CXL.mem capability array header./n"); > + "Couldn't locate the CXL.cache and CXL.mem capability array header.\n"); > return; > } > >
On Mon, Jan 31, 2022 at 6:54 AM Jonathan Cameron <Jonathan.Cameron@huawei.com> wrote: > > On Sun, 23 Jan 2022 16:29:42 -0800 > Dan Williams <dan.j.williams@intel.com> wrote: > > > Fix a '\n' vs '/n' typo. > > > > Fixes: 08422378c4ad ("cxl/pci: Add HDM decoder capabilities") > > Signed-off-by: Dan Williams <dan.j.williams@intel.com> > FWIW > > Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> > Possibly worth pulling this out and sending separately. Yeah, if some other for-5.17 material shows up I might send this along too in advance of v5.18.
On 22-01-23 16:29:42, Dan Williams wrote: > Fix a '\n' vs '/n' typo. > > Fixes: 08422378c4ad ("cxl/pci: Add HDM decoder capabilities") > Signed-off-by: Dan Williams <dan.j.williams@intel.com> Acked-by: Ben Widawsky <ben.widawsky@intel.com [snip]
diff --git a/drivers/cxl/core/regs.c b/drivers/cxl/core/regs.c index 0d63758e2605..12a6cbddf110 100644 --- a/drivers/cxl/core/regs.c +++ b/drivers/cxl/core/regs.c @@ -50,7 +50,7 @@ void cxl_probe_component_regs(struct device *dev, void __iomem *base, if (FIELD_GET(CXL_CM_CAP_HDR_ID_MASK, cap_array) != CM_CAP_HDR_CAP_ID) { dev_err(dev, - "Couldn't locate the CXL.cache and CXL.mem capability array header./n"); + "Couldn't locate the CXL.cache and CXL.mem capability array header.\n"); return; }
Fix a '\n' vs '/n' typo. Fixes: 08422378c4ad ("cxl/pci: Add HDM decoder capabilities") Signed-off-by: Dan Williams <dan.j.williams@intel.com> --- drivers/cxl/core/regs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)