| Message ID | 20211223075640.2924569-1-vladimir.zapolskiy@linaro.org (mailing list archive) |
|---|---|
| State | Accepted |
| Headers | show |
| Series | arm64: dts: qcom: sm8250: add description of dcvsh interrupts | expand |
On Thu, 23 Dec 2021 09:56:40 +0200, Vladimir Zapolskiy wrote: > The change adds SM8250 cpufreq-epss controller interrupts for each > CPU core cluster. > > Applied, thanks! [1/1] arm64: dts: qcom: sm8250: add description of dcvsh interrupts commit: ffd6cc92ab9cb426896481fa8372d38cbe53f76b Best regards,
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 5617a46e5ccd..e7d20c55a743 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -4571,7 +4571,10 @@ cpufreq_hw: cpufreq@18591000 { clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; clock-names = "xo", "alternate"; - + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2"; #freq-domain-cells = <1>; }; };
The change adds SM8250 cpufreq-epss controller interrupts for each CPU core cluster. Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Cc: Thara Gopinath <thara.gopinath@linaro.org> --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-)