| Message ID | 20220121163618.351934-12-heiko@sntech.de (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | riscv: support for svpbmt and D1 memory types | expand |
On Fri, Jan 21, 2022 at 05:36:15PM +0100, Heiko Stuebner wrote: > From: Wei Fu <wefu@redhat.com> > > Previous patch has added svpbmt in arch/riscv and add "riscv,svpmbt" > in the DT mmu node. Update dt-bindings related property here. > > Signed-off-by: Wei Fu <wefu@redhat.com> > Co-developed-by: Guo Ren <guoren@kernel.org> > Signed-off-by: Guo Ren <guoren@kernel.org> > Signed-off-by: Heiko Stuebner <heiko@sntech.de> > Cc: Anup Patel <anup@brainfault.org> > Cc: Palmer Dabbelt <palmer@dabbelt.com> > Cc: Rob Herring <robh+dt@kernel.org> > --- > Documentation/devicetree/bindings/riscv/cpus.yaml | 10 ++++++++++ > 1 file changed, 10 insertions(+) > > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml > index aa5fb64d57eb..3ad2593f1400 100644 > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml > @@ -63,6 +63,16 @@ properties: > - riscv,sv48 > - riscv,none > > + mmu: riscv,mmu > + description: > + Describes the CPU's MMU Standard Extensions support. > + These values originate from the RISC-V Privileged > + Specification document, available from > + https://riscv.org/specifications/ > + $ref: '/schemas/types.yaml#/definitions/string' > + enum: > + - riscv,svpbmt Are there per vendor MMU extensions? If not, drop the 'riscv,' part. > + > riscv,isa: > description: > Identifies the specific RISC-V instruction set architecture > -- > 2.30.2 > >
Am Freitag, 4. Februar 2022, 23:33:42 CET schrieb Rob Herring: > On Fri, Jan 21, 2022 at 05:36:15PM +0100, Heiko Stuebner wrote: > > From: Wei Fu <wefu@redhat.com> > > > > Previous patch has added svpbmt in arch/riscv and add "riscv,svpmbt" > > in the DT mmu node. Update dt-bindings related property here. > > > > Signed-off-by: Wei Fu <wefu@redhat.com> > > Co-developed-by: Guo Ren <guoren@kernel.org> > > Signed-off-by: Guo Ren <guoren@kernel.org> > > Signed-off-by: Heiko Stuebner <heiko@sntech.de> > > Cc: Anup Patel <anup@brainfault.org> > > Cc: Palmer Dabbelt <palmer@dabbelt.com> > > Cc: Rob Herring <robh+dt@kernel.org> > > --- > > Documentation/devicetree/bindings/riscv/cpus.yaml | 10 ++++++++++ > > 1 file changed, 10 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml > > index aa5fb64d57eb..3ad2593f1400 100644 > > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml > > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml > > @@ -63,6 +63,16 @@ properties: > > - riscv,sv48 > > - riscv,none > > > > + mmu: > > riscv,mmu > > > + description: > > + Describes the CPU's MMU Standard Extensions support. > > + These values originate from the RISC-V Privileged > > + Specification document, available from > > + https://riscv.org/specifications/ > > + $ref: '/schemas/types.yaml#/definitions/string' > > + enum: > > + - riscv,svpbmt > > Are there per vendor MMU extensions? If not, drop the 'riscv,' part. Judging by the somewhat wild-west nature, I guess there might already be non-riscv extensions existing somewhere, or at least the probability is quite high that there will be in the future ;-) > > > + > > riscv,isa: > > description: > > Identifies the specific RISC-V instruction set architecture >
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index aa5fb64d57eb..3ad2593f1400 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -63,6 +63,16 @@ properties: - riscv,sv48 - riscv,none + mmu: + description: + Describes the CPU's MMU Standard Extensions support. + These values originate from the RISC-V Privileged + Specification document, available from + https://riscv.org/specifications/ + $ref: '/schemas/types.yaml#/definitions/string' + enum: + - riscv,svpbmt + riscv,isa: description: Identifies the specific RISC-V instruction set architecture