| Message ID | 20220130211838.8382-3-rick.p.edgecombe@intel.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | Shadow stacks for userspace | expand |
On 1/30/22 13:18, Rick Edgecombe wrote: > +config X86_SHADOW_STACK > + prompt "Intel Shadow Stack" > + def_bool n > + depends on AS_WRUSS > + depends on ARCH_HAS_SHADOW_STACK > + select ARCH_USES_HIGH_VMA_FLAGS > + help > + Shadow Stack protection is a hardware feature that detects function > + return address corruption. This helps mitigate ROP attacks. > + Applications must be enabled to use it, and old userspace does not > + get protection "for free". > + Support for this feature is present on Tiger Lake family of > + processors released in 2020 or later. Enabling this feature > + increases kernel text size by 3.7 KB. I guess the "2020" comment is still OK. But, given that it's on AMD and a could of other Intel models, maybe we should just leave this at: CPUs supporting shadow stacks were first released in 2020. If we say anything. We mostly want folks to just go read the documentation if they needs more details.
On Sun, Jan 30 2022 at 13:18, Rick Edgecombe wrote: > +config ARCH_HAS_SHADOW_STACK > + def_bool n > + > +config X86_SHADOW_STACK > + prompt "Intel Shadow Stack" It's also available on AMD, right? Thanks, tglx
On Mon, Feb 07 2022 at 14:39, Dave Hansen wrote: > On 1/30/22 13:18, Rick Edgecombe wrote: >> +config X86_SHADOW_STACK >> + prompt "Intel Shadow Stack" >> + def_bool n >> + depends on AS_WRUSS >> + depends on ARCH_HAS_SHADOW_STACK >> + select ARCH_USES_HIGH_VMA_FLAGS >> + help >> + Shadow Stack protection is a hardware feature that detects function >> + return address corruption. This helps mitigate ROP attacks. >> + Applications must be enabled to use it, and old userspace does not >> + get protection "for free". >> + Support for this feature is present on Tiger Lake family of >> + processors released in 2020 or later. Enabling this feature >> + increases kernel text size by 3.7 KB. > > I guess the "2020" comment is still OK. But, given that it's on AMD and > a could of other Intel models, maybe we should just leave this at: > > CPUs supporting shadow stacks were first released in 2020. Yes. > If we say anything. We mostly want folks to just go read the > documentation if they needs more details. Also the kernel text size increase blurb is pretty useless as that's a number which is wrong from day one. Thanks, tglx
On Tue, 2022-02-08 at 09:41 +0100, Thomas Gleixner wrote: > On Mon, Feb 07 2022 at 14:39, Dave Hansen wrote: > > > On 1/30/22 13:18, Rick Edgecombe wrote: > > > +config X86_SHADOW_STACK > > > + prompt "Intel Shadow Stack" > > > + def_bool n > > > + depends on AS_WRUSS > > > + depends on ARCH_HAS_SHADOW_STACK > > > + select ARCH_USES_HIGH_VMA_FLAGS > > > + help > > > + Shadow Stack protection is a hardware feature that detects > > > function > > > + return address corruption. This helps mitigate ROP > > > attacks. > > > + Applications must be enabled to use it, and old userspace > > > does not > > > + get protection "for free". > > > + Support for this feature is present on Tiger Lake family > > > of > > > + processors released in 2020 or later. Enabling this > > > feature > > > + increases kernel text size by 3.7 KB. > > > > I guess the "2020" comment is still OK. But, given that it's on > > AMD and > > a could of other Intel models, maybe we should just leave this at: > > > > CPUs supporting shadow stacks were first released in 2020. > > Yes. > > > If we say anything. We mostly want folks to just go read the > > documentation if they needs more details. > > Also the kernel text size increase blurb is pretty useless as that's > a > number which is wrong from day one. Makes sense. Thanks.
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index ebe8fc76949a..b9efa0fd906d 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -26,6 +26,7 @@ config X86_64 depends on 64BIT # Options that are inherently 64-bit kernel only: select ARCH_HAS_GIGANTIC_PAGE + select ARCH_HAS_SHADOW_STACK select ARCH_SUPPORTS_INT128 if CC_HAS_INT128 select ARCH_USE_CMPXCHG_LOCKREF select HAVE_ARCH_SOFT_DIRTY @@ -1940,6 +1941,27 @@ config X86_SGX If unsure, say N. +config ARCH_HAS_SHADOW_STACK + def_bool n + +config X86_SHADOW_STACK + prompt "Intel Shadow Stack" + def_bool n + depends on AS_WRUSS + depends on ARCH_HAS_SHADOW_STACK + select ARCH_USES_HIGH_VMA_FLAGS + help + Shadow Stack protection is a hardware feature that detects function + return address corruption. This helps mitigate ROP attacks. + Applications must be enabled to use it, and old userspace does not + get protection "for free". + Support for this feature is present on Tiger Lake family of + processors released in 2020 or later. Enabling this feature + increases kernel text size by 3.7 KB. + See Documentation/x86/intel_cet.rst for more information. + + If unsure, say N. + config EFI bool "EFI runtime service support" depends on ACPI diff --git a/arch/x86/Kconfig.assembler b/arch/x86/Kconfig.assembler index 26b8c08e2fc4..00c79dd93651 100644 --- a/arch/x86/Kconfig.assembler +++ b/arch/x86/Kconfig.assembler @@ -19,3 +19,8 @@ config AS_TPAUSE def_bool $(as-instr,tpause %ecx) help Supported by binutils >= 2.31.1 and LLVM integrated assembler >= V7 + +config AS_WRUSS + def_bool $(as-instr,wrussq %rax$(comma)(%rbx)) + help + Supported by binutils >= 2.31 and LLVM integrated assembler