diff mbox series

hvf: Enable RDTSCP support

Message ID 20211101054836.21471-1-dirty@apple.com (mailing list archive)
State New, archived
Headers show
Series hvf: Enable RDTSCP support | expand

Commit Message

Cameron Esfahani Nov. 1, 2021, 5:48 a.m. UTC 
Pass through RDPID and RDTSCP support in CPUID if host supports it.
Correctly detect if CPU_BASED_TSC_OFFSET and CPU_BASED2_RDTSCP would
be supported in primary and secondary processor-based VM-execution
controls.  Enable RDTSCP in secondary processor controls if RDTSCP
support is indicated in CPUID.

Signed-off-by: Cameron Esfahani <dirty@apple.com>
---
 target/i386/hvf/hvf.c       | 26 +++++++++++++++++---------
 target/i386/hvf/vmcs.h      |  3 ++-
 target/i386/hvf/x86_cpuid.c |  7 ++++---
 3 files changed, 23 insertions(+), 13 deletions(-)

Comments

Cameron Esfahani Feb. 8, 2022, 9:24 p.m. UTC | #1 
Ping

Cameron

> On Oct 31, 2021, at 10:48 PM, Cameron Esfahani <dirty@apple.com> wrote:
> 
> Pass through RDPID and RDTSCP support in CPUID if host supports it.
> Correctly detect if CPU_BASED_TSC_OFFSET and CPU_BASED2_RDTSCP would
> be supported in primary and secondary processor-based VM-execution
> controls.  Enable RDTSCP in secondary processor controls if RDTSCP
> support is indicated in CPUID.
> 
> Signed-off-by: Cameron Esfahani <dirty@apple.com>
> ---
> target/i386/hvf/hvf.c       | 26 +++++++++++++++++---------
> target/i386/hvf/vmcs.h      |  3 ++-
> target/i386/hvf/x86_cpuid.c |  7 ++++---
> 3 files changed, 23 insertions(+), 13 deletions(-)
> 
> diff --git a/target/i386/hvf/hvf.c b/target/i386/hvf/hvf.c
> index 4ba6e82fab..4712fe66d4 100644
> --- a/target/i386/hvf/hvf.c
> +++ b/target/i386/hvf/hvf.c
> @@ -221,6 +221,7 @@ int hvf_arch_init_vcpu(CPUState *cpu)
> {
>     X86CPU *x86cpu = X86_CPU(cpu);
>     CPUX86State *env = &x86cpu->env;
> +    uint64_t reqCap;
> 
>     init_emu();
>     init_decoder();
> @@ -257,19 +258,26 @@ int hvf_arch_init_vcpu(CPUState *cpu)
>     /* set VMCS control fields */
>     wvmcs(cpu->hvf->fd, VMCS_PIN_BASED_CTLS,
>           cap2ctrl(hvf_state->hvf_caps->vmx_cap_pinbased,
> -          VMCS_PIN_BASED_CTLS_EXTINT |
> -          VMCS_PIN_BASED_CTLS_NMI |
> -          VMCS_PIN_BASED_CTLS_VNMI));
> +                   VMCS_PIN_BASED_CTLS_EXTINT |
> +                   VMCS_PIN_BASED_CTLS_NMI |
> +                   VMCS_PIN_BASED_CTLS_VNMI));
>     wvmcs(cpu->hvf->fd, VMCS_PRI_PROC_BASED_CTLS,
>           cap2ctrl(hvf_state->hvf_caps->vmx_cap_procbased,
> -          VMCS_PRI_PROC_BASED_CTLS_HLT |
> -          VMCS_PRI_PROC_BASED_CTLS_MWAIT |
> -          VMCS_PRI_PROC_BASED_CTLS_TSC_OFFSET |
> -          VMCS_PRI_PROC_BASED_CTLS_TPR_SHADOW) |
> +                   VMCS_PRI_PROC_BASED_CTLS_HLT |
> +                   VMCS_PRI_PROC_BASED_CTLS_MWAIT |
> +                   VMCS_PRI_PROC_BASED_CTLS_TSC_OFFSET |
> +                   VMCS_PRI_PROC_BASED_CTLS_TPR_SHADOW) |
>           VMCS_PRI_PROC_BASED_CTLS_SEC_CONTROL);
> +
> +    reqCap = VMCS_PRI_PROC_BASED2_CTLS_APIC_ACCESSES;
> +
> +    /* Is RDTSCP support in CPUID?  If so, enable it in the VMCS. */
> +    if (hvf_get_supported_cpuid(0x80000001, 0, R_EDX) & CPUID_EXT2_RDTSCP) {
> +        reqCap |= VMCS_PRI_PROC_BASED2_CTLS_RDTSCP;
> +    }
> +
>     wvmcs(cpu->hvf->fd, VMCS_SEC_PROC_BASED_CTLS,
> -          cap2ctrl(hvf_state->hvf_caps->vmx_cap_procbased2,
> -                   VMCS_PRI_PROC_BASED2_CTLS_APIC_ACCESSES));
> +          cap2ctrl(hvf_state->hvf_caps->vmx_cap_procbased2, reqCap));
> 
>     wvmcs(cpu->hvf->fd, VMCS_ENTRY_CTLS, cap2ctrl(hvf_state->hvf_caps->vmx_cap_entry,
>           0));
> diff --git a/target/i386/hvf/vmcs.h b/target/i386/hvf/vmcs.h
> index 42de7ebc3a..bb4c764557 100644
> --- a/target/i386/hvf/vmcs.h
> +++ b/target/i386/hvf/vmcs.h
> @@ -354,7 +354,7 @@
> #define VMCS_PRI_PROC_BASED_CTLS_TSC_OFFSET (1 << 3)
> #define VMCS_PRI_PROC_BASED_CTLS_HLT (1 << 7)
> #define VMCS_PRI_PROC_BASED_CTLS_MWAIT         (1 << 10)
> -#define VMCS_PRI_PROC_BASED_CTLS_TSC           (1 << 12)
> +#define VMCS_PRI_PROC_BASED_CTLS_RDTSC         (1 << 12)
> #define VMCS_PRI_PROC_BASED_CTLS_CR8_LOAD      (1 << 19)
> #define VMCS_PRI_PROC_BASED_CTLS_CR8_STORE     (1 << 20)
> #define VMCS_PRI_PROC_BASED_CTLS_TPR_SHADOW    (1 << 21)
> @@ -362,6 +362,7 @@
> #define VMCS_PRI_PROC_BASED_CTLS_SEC_CONTROL   (1 << 31)
> 
> #define VMCS_PRI_PROC_BASED2_CTLS_APIC_ACCESSES (1 << 0)
> +#define VMCS_PRI_PROC_BASED2_CTLS_RDTSCP        (1 << 3)
> #define VMCS_PRI_PROC_BASED2_CTLS_X2APIC        (1 << 4)
> 
> enum task_switch_reason {
> diff --git a/target/i386/hvf/x86_cpuid.c b/target/i386/hvf/x86_cpuid.c
> index 32b0d131df..b11ddaa349 100644
> --- a/target/i386/hvf/x86_cpuid.c
> +++ b/target/i386/hvf/x86_cpuid.c
> @@ -96,7 +96,8 @@ uint32_t hvf_get_supported_cpuid(uint32_t func, uint32_t idx,
>                 ebx &= ~CPUID_7_0_EBX_INVPCID;
>             }
> 
> -            ecx &= CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_AVX512_VPOPCNTDQ;
> +            ecx &= CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_AVX512_VPOPCNTDQ |
> +                   CPUID_7_0_ECX_RDPID;
>             edx &= CPUID_7_0_EDX_AVX512_4VNNIW | CPUID_7_0_EDX_AVX512_4FMAPS;
>         } else {
>             ebx = 0;
> @@ -133,11 +134,11 @@ uint32_t hvf_get_supported_cpuid(uint32_t func, uint32_t idx,
>                 CPUID_FXSR | CPUID_EXT2_FXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_3DNOWEXT |
>                 CPUID_EXT2_3DNOW | CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX;
>         hv_vmx_read_capability(HV_VMX_CAP_PROCBASED2, &cap);
> -        if (!(cap & CPU_BASED2_RDTSCP)) {
> +        if (!(cap2ctrl(cap, CPU_BASED2_RDTSCP) & CPU_BASED2_RDTSCP)) {
>             edx &= ~CPUID_EXT2_RDTSCP;
>         }
>         hv_vmx_read_capability(HV_VMX_CAP_PROCBASED, &cap);
> -        if (!(cap & CPU_BASED_TSC_OFFSET)) {
> +        if (!(cap2ctrl(cap, CPU_BASED_TSC_OFFSET) & CPU_BASED_TSC_OFFSET)) {
>             edx &= ~CPUID_EXT2_RDTSCP;
>         }
>         ecx &= CPUID_EXT3_LAHF_LM | CPUID_EXT3_CMP_LEG | CPUID_EXT3_CR8LEG |
> -- 
> 2.30.1 (Apple Git-130)
> 
>
diff mbox series

Patch

diff --git a/target/i386/hvf/hvf.c b/target/i386/hvf/hvf.c
index 4ba6e82fab..4712fe66d4 100644
--- a/target/i386/hvf/hvf.c
+++ b/target/i386/hvf/hvf.c
@@ -221,6 +221,7 @@  int hvf_arch_init_vcpu(CPUState *cpu)
 {
     X86CPU *x86cpu = X86_CPU(cpu);
     CPUX86State *env = &x86cpu->env;
+    uint64_t reqCap;
 
     init_emu();
     init_decoder();
@@ -257,19 +258,26 @@  int hvf_arch_init_vcpu(CPUState *cpu)
     /* set VMCS control fields */
     wvmcs(cpu->hvf->fd, VMCS_PIN_BASED_CTLS,
           cap2ctrl(hvf_state->hvf_caps->vmx_cap_pinbased,
-          VMCS_PIN_BASED_CTLS_EXTINT |
-          VMCS_PIN_BASED_CTLS_NMI |
-          VMCS_PIN_BASED_CTLS_VNMI));
+                   VMCS_PIN_BASED_CTLS_EXTINT |
+                   VMCS_PIN_BASED_CTLS_NMI |
+                   VMCS_PIN_BASED_CTLS_VNMI));
     wvmcs(cpu->hvf->fd, VMCS_PRI_PROC_BASED_CTLS,
           cap2ctrl(hvf_state->hvf_caps->vmx_cap_procbased,
-          VMCS_PRI_PROC_BASED_CTLS_HLT |
-          VMCS_PRI_PROC_BASED_CTLS_MWAIT |
-          VMCS_PRI_PROC_BASED_CTLS_TSC_OFFSET |
-          VMCS_PRI_PROC_BASED_CTLS_TPR_SHADOW) |
+                   VMCS_PRI_PROC_BASED_CTLS_HLT |
+                   VMCS_PRI_PROC_BASED_CTLS_MWAIT |
+                   VMCS_PRI_PROC_BASED_CTLS_TSC_OFFSET |
+                   VMCS_PRI_PROC_BASED_CTLS_TPR_SHADOW) |
           VMCS_PRI_PROC_BASED_CTLS_SEC_CONTROL);
+
+    reqCap = VMCS_PRI_PROC_BASED2_CTLS_APIC_ACCESSES;
+
+    /* Is RDTSCP support in CPUID?  If so, enable it in the VMCS. */
+    if (hvf_get_supported_cpuid(0x80000001, 0, R_EDX) & CPUID_EXT2_RDTSCP) {
+        reqCap |= VMCS_PRI_PROC_BASED2_CTLS_RDTSCP;
+    }
+
     wvmcs(cpu->hvf->fd, VMCS_SEC_PROC_BASED_CTLS,
-          cap2ctrl(hvf_state->hvf_caps->vmx_cap_procbased2,
-                   VMCS_PRI_PROC_BASED2_CTLS_APIC_ACCESSES));
+          cap2ctrl(hvf_state->hvf_caps->vmx_cap_procbased2, reqCap));
 
     wvmcs(cpu->hvf->fd, VMCS_ENTRY_CTLS, cap2ctrl(hvf_state->hvf_caps->vmx_cap_entry,
           0));
diff --git a/target/i386/hvf/vmcs.h b/target/i386/hvf/vmcs.h
index 42de7ebc3a..bb4c764557 100644
--- a/target/i386/hvf/vmcs.h
+++ b/target/i386/hvf/vmcs.h
@@ -354,7 +354,7 @@ 
 #define VMCS_PRI_PROC_BASED_CTLS_TSC_OFFSET (1 << 3)
 #define VMCS_PRI_PROC_BASED_CTLS_HLT (1 << 7)
 #define VMCS_PRI_PROC_BASED_CTLS_MWAIT         (1 << 10)
-#define VMCS_PRI_PROC_BASED_CTLS_TSC           (1 << 12)
+#define VMCS_PRI_PROC_BASED_CTLS_RDTSC         (1 << 12)
 #define VMCS_PRI_PROC_BASED_CTLS_CR8_LOAD      (1 << 19)
 #define VMCS_PRI_PROC_BASED_CTLS_CR8_STORE     (1 << 20)
 #define VMCS_PRI_PROC_BASED_CTLS_TPR_SHADOW    (1 << 21)
@@ -362,6 +362,7 @@ 
 #define VMCS_PRI_PROC_BASED_CTLS_SEC_CONTROL   (1 << 31)
 
 #define VMCS_PRI_PROC_BASED2_CTLS_APIC_ACCESSES (1 << 0)
+#define VMCS_PRI_PROC_BASED2_CTLS_RDTSCP        (1 << 3)
 #define VMCS_PRI_PROC_BASED2_CTLS_X2APIC        (1 << 4)
 
 enum task_switch_reason {
diff --git a/target/i386/hvf/x86_cpuid.c b/target/i386/hvf/x86_cpuid.c
index 32b0d131df..b11ddaa349 100644
--- a/target/i386/hvf/x86_cpuid.c
+++ b/target/i386/hvf/x86_cpuid.c
@@ -96,7 +96,8 @@  uint32_t hvf_get_supported_cpuid(uint32_t func, uint32_t idx,
                 ebx &= ~CPUID_7_0_EBX_INVPCID;
             }
 
-            ecx &= CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_AVX512_VPOPCNTDQ;
+            ecx &= CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_AVX512_VPOPCNTDQ |
+                   CPUID_7_0_ECX_RDPID;
             edx &= CPUID_7_0_EDX_AVX512_4VNNIW | CPUID_7_0_EDX_AVX512_4FMAPS;
         } else {
             ebx = 0;
@@ -133,11 +134,11 @@  uint32_t hvf_get_supported_cpuid(uint32_t func, uint32_t idx,
                 CPUID_FXSR | CPUID_EXT2_FXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_3DNOWEXT |
                 CPUID_EXT2_3DNOW | CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX;
         hv_vmx_read_capability(HV_VMX_CAP_PROCBASED2, &cap);
-        if (!(cap & CPU_BASED2_RDTSCP)) {
+        if (!(cap2ctrl(cap, CPU_BASED2_RDTSCP) & CPU_BASED2_RDTSCP)) {
             edx &= ~CPUID_EXT2_RDTSCP;
         }
         hv_vmx_read_capability(HV_VMX_CAP_PROCBASED, &cap);
-        if (!(cap & CPU_BASED_TSC_OFFSET)) {
+        if (!(cap2ctrl(cap, CPU_BASED_TSC_OFFSET) & CPU_BASED_TSC_OFFSET)) {
             edx &= ~CPUID_EXT2_RDTSCP;
         }
         ecx &= CPUID_EXT3_LAHF_LM | CPUID_EXT3_CMP_LEG | CPUID_EXT3_CR8LEG |