diff mbox series

[1/4] hw/openrisc/openrisc_sim: Create machine state for or1ksim

Message ID 20220210063009.1048751-2-shorne@gmail.com (mailing list archive)
State New, archived
Headers show
Series OpenRISC Device Tree Support | expand

Commit Message

Stafford Horne Feb. 10, 2022, 6:30 a.m. UTC
This will allow us to attach machine state attributes like
the device tree fdt.

Signed-off-by: Stafford Horne <shorne@gmail.com>
---
 hw/openrisc/openrisc_sim.c | 31 +++++++++++++++++++++++++++++--
 1 file changed, 29 insertions(+), 2 deletions(-)

Comments

Philippe Mathieu-Daudé Feb. 10, 2022, 11:05 a.m. UTC | #1
On 10/2/22 07:30, Stafford Horne wrote:
> This will allow us to attach machine state attributes like
> the device tree fdt.
> 
> Signed-off-by: Stafford Horne <shorne@gmail.com>
> ---
>   hw/openrisc/openrisc_sim.c | 31 +++++++++++++++++++++++++++++--
>   1 file changed, 29 insertions(+), 2 deletions(-)

> @@ -141,6 +153,7 @@ static void openrisc_sim_init(MachineState *machine)
>       ram_addr_t ram_size = machine->ram_size;
>       const char *kernel_filename = machine->kernel_filename;
>       OpenRISCCPU *cpus[2] = {};
> +    Or1ksimState *s = OR1KSIM_MACHINE(machine);

This change belong to patch #3.

Otherwise:
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

>       MemoryRegion *ram;
>       qemu_irq serial_irq;
>       int n;
> @@ -183,8 +196,10 @@ static void openrisc_sim_init(MachineState *machine)
>       openrisc_load_kernel(ram_size, kernel_filename);
>   }
Stafford Horne Feb. 10, 2022, 12:16 p.m. UTC | #2
On Thu, Feb 10, 2022 at 12:05:22PM +0100, Philippe Mathieu-Daudé wrote:
> On 10/2/22 07:30, Stafford Horne wrote:
> > This will allow us to attach machine state attributes like
> > the device tree fdt.
> > 
> > Signed-off-by: Stafford Horne <shorne@gmail.com>
> > ---
> >   hw/openrisc/openrisc_sim.c | 31 +++++++++++++++++++++++++++++--
> >   1 file changed, 29 insertions(+), 2 deletions(-)
> 
> > @@ -141,6 +153,7 @@ static void openrisc_sim_init(MachineState *machine)
> >       ram_addr_t ram_size = machine->ram_size;
> >       const char *kernel_filename = machine->kernel_filename;
> >       OpenRISCCPU *cpus[2] = {};
> > +    Or1ksimState *s = OR1KSIM_MACHINE(machine);
> 
> This change belong to patch #3.

Yes, when I was splitting this patch out I left it here because I was
"preparing".  But it is not being used, so fair enough.

> Otherwise:
> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Thanks

> >       MemoryRegion *ram;
> >       qemu_irq serial_irq;
> >       int n;
> > @@ -183,8 +196,10 @@ static void openrisc_sim_init(MachineState *machine)
> >       openrisc_load_kernel(ram_size, kernel_filename);
> >   }
diff mbox series

Patch

diff --git a/hw/openrisc/openrisc_sim.c b/hw/openrisc/openrisc_sim.c
index 73fe383c2d..b83cc1c191 100644
--- a/hw/openrisc/openrisc_sim.c
+++ b/hw/openrisc/openrisc_sim.c
@@ -37,6 +37,18 @@ 
 
 #define KERNEL_LOAD_ADDR 0x100
 
+#define TYPE_OR1KSIM_MACHINE MACHINE_TYPE_NAME("or1k-sim")
+#define OR1KSIM_MACHINE(obj) \
+    OBJECT_CHECK(Or1ksimState, (obj), TYPE_OR1KSIM_MACHINE)
+
+typedef struct Or1ksimState {
+    /*< private >*/
+    MachineState parent_obj;
+
+    /*< public >*/
+
+} Or1ksimState;
+
 static struct openrisc_boot_info {
     uint32_t bootstrap_pc;
 } boot_info;
@@ -141,6 +153,7 @@  static void openrisc_sim_init(MachineState *machine)
     ram_addr_t ram_size = machine->ram_size;
     const char *kernel_filename = machine->kernel_filename;
     OpenRISCCPU *cpus[2] = {};
+    Or1ksimState *s = OR1KSIM_MACHINE(machine);
     MemoryRegion *ram;
     qemu_irq serial_irq;
     int n;
@@ -183,8 +196,10 @@  static void openrisc_sim_init(MachineState *machine)
     openrisc_load_kernel(ram_size, kernel_filename);
 }
 
-static void openrisc_sim_machine_init(MachineClass *mc)
+static void openrisc_sim_machine_init(ObjectClass *oc, void *data)
 {
+    MachineClass *mc = MACHINE_CLASS(oc);
+
     mc->desc = "or1k simulation";
     mc->init = openrisc_sim_init;
     mc->max_cpus = 2;
@@ -192,4 +207,16 @@  static void openrisc_sim_machine_init(MachineClass *mc)
     mc->default_cpu_type = OPENRISC_CPU_TYPE_NAME("or1200");
 }
 
-DEFINE_MACHINE("or1k-sim", openrisc_sim_machine_init)
+static const TypeInfo or1ksim_machine_typeinfo = {
+    .name       = TYPE_OR1KSIM_MACHINE,
+    .parent     = TYPE_MACHINE,
+    .class_init = openrisc_sim_machine_init,
+    .instance_size = sizeof(Or1ksimState),
+};
+
+static void or1ksim_machine_init_register_types(void)
+{
+    type_register_static(&or1ksim_machine_typeinfo);
+}
+
+type_init(or1ksim_machine_init_register_types)