diff mbox series

[V11,16/19] arm64: dts: mt8183: add dvfsrc related nodes

Message ID 20210812085846.2628-17-dawei.chien@mediatek.com (mailing list archive)
State New, archived
Headers show
Series Add driver for dvfsrc, support for interconnect | expand

Commit Message

Dawei Chien Aug. 12, 2021, 8:58 a.m. UTC 
From: Henry Chen <henryc.chen@mediatek.com>

Add DDR EMI provider dictating dram interconnect bus performance found on
MT8192-based platforms

Signed-off-by: Henry Chen <henryc.chen@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8183.dtsi | 2 ++
 1 file changed, 2 insertions(+)

Comments

AngeloGioacchino Del Regno Feb. 3, 2022, 3:16 p.m. UTC | #1 
Il 12/08/21 10:58, Dawei Chien ha scritto:
> From: Henry Chen <henryc.chen@mediatek.com>
> 
> Add DDR EMI provider dictating dram interconnect bus performance found on
> MT8192-based platforms
> 
> Signed-off-by: Henry Chen <henryc.chen@mediatek.com>

This patch definitely has to be squashed with patch 07/19.

Same for patch 17 and 19.

Also, sign-off.

> ---
>   arch/arm64/boot/dts/mediatek/mt8183.dtsi | 2 ++
>   1 file changed, 2 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> index 7ad4cf646579..86f85c34c88a 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> @@ -7,6 +7,7 @@
>   
>   #include <dt-bindings/clock/mt8183-clk.h>
>   #include <dt-bindings/gce/mt8183-gce.h>
> +#include <dt-bindings/interconnect/mtk,mt8183-emi.h>
>   #include <dt-bindings/interrupt-controller/arm-gic.h>
>   #include <dt-bindings/interrupt-controller/irq.h>
>   #include <dt-bindings/memory/mt8183-larb-port.h>
> @@ -586,6 +587,7 @@
>   		ddr_emi: dvfsrc@10012000 {
>   			compatible = "mediatek,mt8183-dvfsrc";
>   			reg = <0 0x10012000 0 0x1000>;
> +			#interconnect-cells = <1>;
>   		};
>   
>   		pwrap: pwrap@1000d000 {
Dawei Chien Feb. 11, 2022, 3:50 a.m. UTC | #2 
On Thu, 2022-02-03 at 16:16 +0100, AngeloGioacchino Del Regno wrote:
> Il 12/08/21 10:58, Dawei Chien ha scritto:
> > From: Henry Chen <henryc.chen@mediatek.com>
> > 
> > Add DDR EMI provider dictating dram interconnect bus performance
> > found on
> > MT8192-based platforms
> > 
> > Signed-off-by: Henry Chen <henryc.chen@mediatek.com>
> 
> This patch definitely has to be squashed with patch 07/19.
> 
> Same for patch 17 and 19.
> 
> Also, sign-off.
> 

I would squash patch 07/16, 08/17, 09/18 on next version, thank you.

> > ---
> >   arch/arm64/boot/dts/mediatek/mt8183.dtsi | 2 ++
> >   1 file changed, 2 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> > index 7ad4cf646579..86f85c34c88a 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> > @@ -7,6 +7,7 @@
> >   
> >   #include <dt-bindings/clock/mt8183-clk.h>
> >   #include <dt-bindings/gce/mt8183-gce.h>
> > +#include <dt-bindings/interconnect/mtk,mt8183-emi.h>
> >   #include <dt-bindings/interrupt-controller/arm-gic.h>
> >   #include <dt-bindings/interrupt-controller/irq.h>
> >   #include <dt-bindings/memory/mt8183-larb-port.h>
> > @@ -586,6 +587,7 @@
> >   		ddr_emi: dvfsrc@10012000 {
> >   			compatible = "mediatek,mt8183-dvfsrc";
> >   			reg = <0 0x10012000 0 0x1000>;
> > +			#interconnect-cells = <1>;
> >   		};
> >   
> >   		pwrap: pwrap@1000d000 {
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index 7ad4cf646579..86f85c34c88a 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -7,6 +7,7 @@ 
 
 #include <dt-bindings/clock/mt8183-clk.h>
 #include <dt-bindings/gce/mt8183-gce.h>
+#include <dt-bindings/interconnect/mtk,mt8183-emi.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/memory/mt8183-larb-port.h>
@@ -586,6 +587,7 @@ 
 		ddr_emi: dvfsrc@10012000 {
 			compatible = "mediatek,mt8183-dvfsrc";
 			reg = <0 0x10012000 0 0x1000>;
+			#interconnect-cells = <1>;
 		};
 
 		pwrap: pwrap@1000d000 {