| Message ID | 20220205162144.30240-4-vidyas@nvidia.com (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Lorenzo Pieralisi |
| Headers | show |
| Series | PCI: tegra: Add Tegra234 PCIe support | expand |
On 05/02/2022 17:21, Vidya Sagar wrote: > Add the memory client and stream ID definitions for the PCIe hardware > found on Tegra234 SoCs. I could not find dependencies or merging strategy in cover letter. Please always describe it, so I don't have to go through all the patches to figure this out. > > Signed-off-by: Vidya Sagar <vidyas@nvidia.com> > --- > include/dt-bindings/memory/tegra234-mc.h | 64 ++++++++++++++++++++++++ > 1 file changed, 64 insertions(+) > > diff --git a/include/dt-bindings/memory/tegra234-mc.h b/include/dt-bindings/memory/tegra234-mc.h > index 2662f70c15c6..60017684858a 100644 > --- a/include/dt-bindings/memory/tegra234-mc.h > +++ b/include/dt-bindings/memory/tegra234-mc.h > @@ -7,15 +7,53 @@ > #define TEGRA234_SID_INVALID 0x00 > #define TEGRA234_SID_PASSTHROUGH 0x7f > > +/* NISO0 stream IDs */ > +#define TEGRA234_SID_PCIE0 0x12U > +#define TEGRA234_SID_PCIE4 0x13U > +#define TEGRA234_SID_PCIE5 0x14U > +#define TEGRA234_SID_PCIE6 0x15U > +#define TEGRA234_SID_PCIE9 0x1FU > > /* NISO1 stream IDs */ > #define TEGRA234_SID_SDMMC4 0x02 > +#define TEGRA234_SID_PCIE1 0x5U > +#define TEGRA234_SID_PCIE2 0x6U > +#define TEGRA234_SID_PCIE3 0x7U > +#define TEGRA234_SID_PCIE7 0x8U > +#define TEGRA234_SID_PCIE8 0x9U > +#define TEGRA234_SID_PCIE10 0xBU I don't see usage of these... > #define TEGRA234_SID_BPMP 0x10 > > /* > * memory client IDs > */ > > +/* PCIE6 read clients */ > +#define TEGRA234_MEMORY_CLIENT_PCIE6AR 0x28 I see you use them in DTS but not in mc driver. Don't you miss anything here? > +/* PCIE6 write clients */ > +#define TEGRA234_MEMORY_CLIENT_PCIE6AW 0x29 > +/* PCIE7 read clients */ > +#define TEGRA234_MEMORY_ Best regards, Krzysztof
On Sat, 05 Feb 2022 21:51:37 +0530, Vidya Sagar wrote: > Add the memory client and stream ID definitions for the PCIe hardware > found on Tegra234 SoCs. > > Signed-off-by: Vidya Sagar <vidyas@nvidia.com> > --- > include/dt-bindings/memory/tegra234-mc.h | 64 ++++++++++++++++++++++++ > 1 file changed, 64 insertions(+) > Acked-by: Rob Herring <robh@kernel.org>
On Sun, Feb 06, 2022 at 12:33:27PM +0100, Krzysztof Kozlowski wrote: > On 05/02/2022 17:21, Vidya Sagar wrote: > > Add the memory client and stream ID definitions for the PCIe hardware > > found on Tegra234 SoCs. > > I could not find dependencies or merging strategy in cover letter. > Please always describe it, so I don't have to go through all the patches > to figure this out. > > > > > Signed-off-by: Vidya Sagar <vidyas@nvidia.com> > > --- > > include/dt-bindings/memory/tegra234-mc.h | 64 ++++++++++++++++++++++++ > > 1 file changed, 64 insertions(+) > > > > diff --git a/include/dt-bindings/memory/tegra234-mc.h b/include/dt-bindings/memory/tegra234-mc.h > > index 2662f70c15c6..60017684858a 100644 > > --- a/include/dt-bindings/memory/tegra234-mc.h > > +++ b/include/dt-bindings/memory/tegra234-mc.h > > @@ -7,15 +7,53 @@ > > #define TEGRA234_SID_INVALID 0x00 > > #define TEGRA234_SID_PASSTHROUGH 0x7f > > > > +/* NISO0 stream IDs */ > > +#define TEGRA234_SID_PCIE0 0x12U > > +#define TEGRA234_SID_PCIE4 0x13U > > +#define TEGRA234_SID_PCIE5 0x14U > > +#define TEGRA234_SID_PCIE6 0x15U > > +#define TEGRA234_SID_PCIE9 0x1FU > > > > /* NISO1 stream IDs */ > > #define TEGRA234_SID_SDMMC4 0x02 > > +#define TEGRA234_SID_PCIE1 0x5U > > +#define TEGRA234_SID_PCIE2 0x6U > > +#define TEGRA234_SID_PCIE3 0x7U > > +#define TEGRA234_SID_PCIE7 0x8U > > +#define TEGRA234_SID_PCIE8 0x9U > > +#define TEGRA234_SID_PCIE10 0xBU > > I don't see usage of these... > > > #define TEGRA234_SID_BPMP 0x10 > > > > /* > > * memory client IDs > > */ > > > > +/* PCIE6 read clients */ > > +#define TEGRA234_MEMORY_CLIENT_PCIE6AR 0x28 > > I see you use them in DTS but not in mc driver. Don't you miss anything > here? This is along the same lines as the APE and HDA patches earlier, so I would expect Vidya to add a memory controller patch that makes use of these once the initial Tegra234 memory controller patch was merged. Meanwhile, I've applied this to the Tegra tree, on top of the other patches that add memory client definitions and resolved the conflicts that ensued. That way, by the time we get around to the next cycle all of these dependencies will exist and applying the memory controller patches should become easier. Thierry
diff --git a/include/dt-bindings/memory/tegra234-mc.h b/include/dt-bindings/memory/tegra234-mc.h index 2662f70c15c6..60017684858a 100644 --- a/include/dt-bindings/memory/tegra234-mc.h +++ b/include/dt-bindings/memory/tegra234-mc.h @@ -7,15 +7,53 @@ #define TEGRA234_SID_INVALID 0x00 #define TEGRA234_SID_PASSTHROUGH 0x7f +/* NISO0 stream IDs */ +#define TEGRA234_SID_PCIE0 0x12U +#define TEGRA234_SID_PCIE4 0x13U +#define TEGRA234_SID_PCIE5 0x14U +#define TEGRA234_SID_PCIE6 0x15U +#define TEGRA234_SID_PCIE9 0x1FU /* NISO1 stream IDs */ #define TEGRA234_SID_SDMMC4 0x02 +#define TEGRA234_SID_PCIE1 0x5U +#define TEGRA234_SID_PCIE2 0x6U +#define TEGRA234_SID_PCIE3 0x7U +#define TEGRA234_SID_PCIE7 0x8U +#define TEGRA234_SID_PCIE8 0x9U +#define TEGRA234_SID_PCIE10 0xBU #define TEGRA234_SID_BPMP 0x10 /* * memory client IDs */ +/* PCIE6 read clients */ +#define TEGRA234_MEMORY_CLIENT_PCIE6AR 0x28 +/* PCIE6 write clients */ +#define TEGRA234_MEMORY_CLIENT_PCIE6AW 0x29 +/* PCIE7 read clients */ +#define TEGRA234_MEMORY_CLIENT_PCIE7AR 0x2a +/* PCIE7 write clients */ +#define TEGRA234_MEMORY_CLIENT_PCIE7AW 0x30 +/* PCIE8 read clients */ +#define TEGRA234_MEMORY_CLIENT_PCIE8AR 0x32 +/* PCIE8 write clients */ +#define TEGRA234_MEMORY_CLIENT_PCIE8AW 0x3b +/* PCIE9 read clients */ +#define TEGRA234_MEMORY_CLIENT_PCIE9AR 0x3c +/* PCIE6r1 read clients */ +#define TEGRA234_MEMORY_CLIENT_PCIE6AR1 0x3d +/* PCIE9 write clients */ +#define TEGRA234_MEMORY_CLIENT_PCIE9AW 0x3e +/* PCIE10 read clients */ +#define TEGRA234_MEMORY_CLIENT_PCIE10AR 0x3f +/* PCIE10 write clients */ +#define TEGRA234_MEMORY_CLIENT_PCIE10AW 0x40 +/* PCIE10r1 read clients */ +#define TEGRA234_MEMORY_CLIENT_PCIE10AR1 0x48 +/* PCIE7r1 read clients */ +#define TEGRA234_MEMORY_CLIENT_PCIE7AR1 0x49 /* sdmmcd memory read client */ #define TEGRA234_MEMORY_CLIENT_SDMMCRAB 0x63 /* sdmmcd memory write client */ @@ -28,5 +66,31 @@ #define TEGRA234_MEMORY_CLIENT_BPMPDMAR 0x95 /* BPMPDMA write client */ #define TEGRA234_MEMORY_CLIENT_BPMPDMAW 0x96 +/* PCIE0 read clients */ +#define TEGRA234_MEMORY_CLIENT_PCIE0R 0xd8 +/* PCIE0 write clients */ +#define TEGRA234_MEMORY_CLIENT_PCIE0W 0xd9 +/* PCIE1 read clients */ +#define TEGRA234_MEMORY_CLIENT_PCIE1R 0xda +/* PCIE1 write clients */ +#define TEGRA234_MEMORY_CLIENT_PCIE1W 0xdb +/* PCIE2 read clients */ +#define TEGRA234_MEMORY_CLIENT_PCIE2AR 0xdc +/* PCIE2 write clients */ +#define TEGRA234_MEMORY_CLIENT_PCIE2AW 0xdd +/* PCIE3 read clients */ +#define TEGRA234_MEMORY_CLIENT_PCIE3R 0xde +/* PCIE3 write clients */ +#define TEGRA234_MEMORY_CLIENT_PCIE3W 0xdf +/* PCIE4 read clients */ +#define TEGRA234_MEMORY_CLIENT_PCIE4R 0xe0 +/* PCIE4 write clients */ +#define TEGRA234_MEMORY_CLIENT_PCIE4W 0xe1 +/* PCIE5 read clients */ +#define TEGRA234_MEMORY_CLIENT_PCIE5R 0xe2 +/* PCIE5 write clients */ +#define TEGRA234_MEMORY_CLIENT_PCIE5W 0xe3 +/* PCIE5r1 read clients */ +#define TEGRA234_MEMORY_CLIENT_PCIE5R1 0xef #endif
Add the memory client and stream ID definitions for the PCIe hardware found on Tegra234 SoCs. Signed-off-by: Vidya Sagar <vidyas@nvidia.com> --- include/dt-bindings/memory/tegra234-mc.h | 64 ++++++++++++++++++++++++ 1 file changed, 64 insertions(+)