| Message ID | 20220205162144.30240-5-vidyas@nvidia.com (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Lorenzo Pieralisi |
| Headers | show |
| Series | PCI: tegra: Add Tegra234 PCIe support | expand |
On 2022-02-05 18:21, Vidya Sagar wrote: > Subject: > [PATCH V1 04/10] dt-bindings: PHY: P2U: Add support for Tegra234 P2U block > From: > Vidya Sagar <vidyas@nvidia.com> > Date: > 2022-02-05, 18:21 > > To: > <bhelgaas@google.com>, <lorenzo.pieralisi@arm.com>, > <robh+dt@kernel.org>, <thierry.reding@gmail.com>, <jonathanh@nvidia.com> > CC: > <kishon@ti.com>, <vkoul@kernel.org>, <kw@linux.com>, > <krzysztof.kozlowski@canonical.com>, <p.zabel@pengutronix.de>, > <mperttunen@nvidia.com>, <linux-pci@vger.kernel.org>, > <devicetree@vger.kernel.org>, <linux-tegra@vger.kernel.org>, > <linux-kernel@vger.kernel.org>, <linux-phy@lists.infradead.org>, > <kthota@nvidia.com>, <mmaddireddy@nvidia.com>, <vidyas@nvidia.com>, > <sagar.tv@gmail.com> > > > Add support for Tegra234 P2U (PIPE to UPHY) module block which is a glue > module instantiated once for each PCIe lane between Synopsys DesignWare > core based PCIe IP and Universal PHY block. > > Signed-off-by: Vidya Sagar<vidyas@nvidia.com> > --- > .../bindings/phy/phy-tegra194-p2u.yaml | 17 +++++++++++++---- > 1 file changed, 13 insertions(+), 4 deletions(-) > > diff --git a/Documentation/devicetree/bindings/phy/phy-tegra194-p2u.yaml b/Documentation/devicetree/bindings/phy/phy-tegra194-p2u.yaml > index 9a89d05efbda..6ba1f69b1126 100644 > --- a/Documentation/devicetree/bindings/phy/phy-tegra194-p2u.yaml > +++ b/Documentation/devicetree/bindings/phy/phy-tegra194-p2u.yaml > @@ -4,7 +4,7 @@ > $id:"http://devicetree.org/schemas/phy/phy-tegra194-p2u.yaml#" > $schema:"http://devicetree.org/meta-schemas/core.yaml#" > > -title: NVIDIA Tegra194 P2U binding > +title: NVIDIA Tegra194 & Tegra234 P2U binding > > maintainers: > - Thierry Reding<treding@nvidia.com> > @@ -12,13 +12,17 @@ maintainers: > description: > > Tegra194 has two PHY bricks namely HSIO (High Speed IO) and NVHS (NVIDIA High > Speed) each interfacing with 12 and 8 P2U instances respectively. > + Tegra234 has three PHY bricks namesly HSIO, NVHS and GBE (Gigabit Ethernet) typo: namely
On Sat, Feb 05, 2022 at 09:51:38PM +0530, Vidya Sagar wrote: > Add support for Tegra234 P2U (PIPE to UPHY) module block which is a glue > module instantiated once for each PCIe lane between Synopsys DesignWare > core based PCIe IP and Universal PHY block. > > Signed-off-by: Vidya Sagar <vidyas@nvidia.com> > --- > .../bindings/phy/phy-tegra194-p2u.yaml | 17 +++++++++++++---- > 1 file changed, 13 insertions(+), 4 deletions(-) > > diff --git a/Documentation/devicetree/bindings/phy/phy-tegra194-p2u.yaml b/Documentation/devicetree/bindings/phy/phy-tegra194-p2u.yaml > index 9a89d05efbda..6ba1f69b1126 100644 > --- a/Documentation/devicetree/bindings/phy/phy-tegra194-p2u.yaml > +++ b/Documentation/devicetree/bindings/phy/phy-tegra194-p2u.yaml > @@ -4,7 +4,7 @@ > $id: "http://devicetree.org/schemas/phy/phy-tegra194-p2u.yaml#" > $schema: "http://devicetree.org/meta-schemas/core.yaml#" > > -title: NVIDIA Tegra194 P2U binding > +title: NVIDIA Tegra194 & Tegra234 P2U binding > > maintainers: > - Thierry Reding <treding@nvidia.com> > @@ -12,13 +12,17 @@ maintainers: > description: > > Tegra194 has two PHY bricks namely HSIO (High Speed IO) and NVHS (NVIDIA High > Speed) each interfacing with 12 and 8 P2U instances respectively. > + Tegra234 has three PHY bricks namesly HSIO, NVHS and GBE (Gigabit Ethernet) > + each interfacing with 8, 8 and 8 P2U instances respectively. > A P2U instance is a glue logic between Synopsys DesignWare Core PCIe IP's PIPE > - interface and PHY of HSIO/NVHS bricks. Each P2U instance represents one PCIe > - lane. > + interface and PHY of HSIO/NVHS/GBE bricks. Each P2U instance represents one > + PCIe lane. > > properties: > compatible: > - const: nvidia,tegra194-p2u > + oneOf: > + - const: nvidia,tegra194-p2u > + - const: nvidia,tegra234-p2u Use 'enum' > > reg: > maxItems: 1 > @@ -28,6 +32,11 @@ properties: > items: > - const: ctl > > + nvidia,skip-sz-protect-en: > + description: Should be present if two PCIe retimers are present between > + the root port and its immediate downstream device. > + type: boolean Check your indentation. This patch should have failed checks for both of these issues. No report so either this patch couldn't be applied or there another issue. In any case, you failed to test this yourself. Rob
diff --git a/Documentation/devicetree/bindings/phy/phy-tegra194-p2u.yaml b/Documentation/devicetree/bindings/phy/phy-tegra194-p2u.yaml index 9a89d05efbda..6ba1f69b1126 100644 --- a/Documentation/devicetree/bindings/phy/phy-tegra194-p2u.yaml +++ b/Documentation/devicetree/bindings/phy/phy-tegra194-p2u.yaml @@ -4,7 +4,7 @@ $id: "http://devicetree.org/schemas/phy/phy-tegra194-p2u.yaml#" $schema: "http://devicetree.org/meta-schemas/core.yaml#" -title: NVIDIA Tegra194 P2U binding +title: NVIDIA Tegra194 & Tegra234 P2U binding maintainers: - Thierry Reding <treding@nvidia.com> @@ -12,13 +12,17 @@ maintainers: description: > Tegra194 has two PHY bricks namely HSIO (High Speed IO) and NVHS (NVIDIA High Speed) each interfacing with 12 and 8 P2U instances respectively. + Tegra234 has three PHY bricks namesly HSIO, NVHS and GBE (Gigabit Ethernet) + each interfacing with 8, 8 and 8 P2U instances respectively. A P2U instance is a glue logic between Synopsys DesignWare Core PCIe IP's PIPE - interface and PHY of HSIO/NVHS bricks. Each P2U instance represents one PCIe - lane. + interface and PHY of HSIO/NVHS/GBE bricks. Each P2U instance represents one + PCIe lane. properties: compatible: - const: nvidia,tegra194-p2u + oneOf: + - const: nvidia,tegra194-p2u + - const: nvidia,tegra234-p2u reg: maxItems: 1 @@ -28,6 +32,11 @@ properties: items: - const: ctl + nvidia,skip-sz-protect-en: + description: Should be present if two PCIe retimers are present between + the root port and its immediate downstream device. + type: boolean + '#phy-cells': const: 0
Add support for Tegra234 P2U (PIPE to UPHY) module block which is a glue module instantiated once for each PCIe lane between Synopsys DesignWare core based PCIe IP and Universal PHY block. Signed-off-by: Vidya Sagar <vidyas@nvidia.com> --- .../bindings/phy/phy-tegra194-p2u.yaml | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-)