| Message ID | 20220211004203.14915-1-zev@bewilderbeest.net (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v2] serial: 8250_aspeed_vuart: add PORT_ASPEED_VUART port type | expand |
On Thu, Feb 10, 2022 at 04:42:03PM -0800, Zev Weiss wrote: > Commit 54da3e381c2b ("serial: 8250_aspeed_vuart: use UPF_IOREMAP to > set up register mapping") fixed a bug that had, as a side-effect, > prevented the 8250_aspeed_vuart driver from enabling the VUART's > FIFOs. However, fixing that (and hence enabling the FIFOs) has in > turn revealed what appears to be a hardware bug in the ASPEED VUART in > which the host-side THRE bit doesn't get if the BMC-side receive FIFO > trigger level is set to anything but one byte. This causes problems > for polled-mode writes from the host -- for example, Linux kernel > console writes proceed at a glacial pace (less than 100 bytes per > second) because the write path waits for a 10ms timeout to expire > after every character instead of being able to continue on to the next > character upon seeing THRE asserted. (GRUB behaves similarly.) > > As a workaround, introduce a new port type for the ASPEED VUART that's > identical to PORT_16550A as it had previously been using, but with > UART_FCR_R_TRIG_00 instead to set the receive FIFO trigger level to > one byte, which (experimentally) seems to avoid the problematic THRE > behavior. ... > + [PORT_ASPEED_VUART] = { > + .name = "ASPEED VUART", > + .fifo_size = 16, > + .tx_loadsz = 16, > + .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00, > + .rxtrig_bytes = {1, 4, 8, 14}, > + .flags = UART_CAP_FIFO, > + }, This is quite similar to AR7 type. Can that be (re-)used?
On Fri, Feb 11, 2022 at 02:19:12AM PST, Andy Shevchenko wrote: >On Thu, Feb 10, 2022 at 04:42:03PM -0800, Zev Weiss wrote: >> Commit 54da3e381c2b ("serial: 8250_aspeed_vuart: use UPF_IOREMAP to >> set up register mapping") fixed a bug that had, as a side-effect, >> prevented the 8250_aspeed_vuart driver from enabling the VUART's >> FIFOs. However, fixing that (and hence enabling the FIFOs) has in >> turn revealed what appears to be a hardware bug in the ASPEED VUART in >> which the host-side THRE bit doesn't get if the BMC-side receive FIFO >> trigger level is set to anything but one byte. This causes problems >> for polled-mode writes from the host -- for example, Linux kernel >> console writes proceed at a glacial pace (less than 100 bytes per >> second) because the write path waits for a 10ms timeout to expire >> after every character instead of being able to continue on to the next >> character upon seeing THRE asserted. (GRUB behaves similarly.) >> >> As a workaround, introduce a new port type for the ASPEED VUART that's >> identical to PORT_16550A as it had previously been using, but with >> UART_FCR_R_TRIG_00 instead to set the receive FIFO trigger level to >> one byte, which (experimentally) seems to avoid the problematic THRE >> behavior. > >... > >> + [PORT_ASPEED_VUART] = { >> + .name = "ASPEED VUART", >> + .fifo_size = 16, >> + .tx_loadsz = 16, >> + .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00, >> + .rxtrig_bytes = {1, 4, 8, 14}, >> + .flags = UART_CAP_FIFO, >> + }, > >This is quite similar to AR7 type. Can that be (re-)used? > I suppose that could work if there's a strong preference for it, but I'd sort of prefer to keep it as a separate entry if that's alright. Firstly, I haven't yet heard back from ASPEED confirming the nature of the underlying problem, so it seems entirely possible we'll end up wanting to tweak it further if they can suggest a better workaround, and I believe having rxtrig_bytes defined (which AR7 doesn't) enables adjusting the trigger-level FCR bits from userspace via sysfs, which could be useful for experiments relating to that. Secondly, there are a half-dozen or so other existing entries in the uart_config[] array that differ only in name, so it doesn't seem to be something that's generally been deemed worth optimizing thus far, and now that the constant value has been shifted down it's just filling in a previously-empty slot in the array instead of expanding it further. But mostly it strikes me as a bit...gratuitously confusing to label the port as something it ultimately isn't, even if they're functionally "close enough" (calling it an 8250 or 16550A is a bit different, as those are well-established, widely-emulated ones that have become generic nomenclature, which isn't so much the case for AR7). While in the source code it could be explained with a comment, having /proc/tty/driver/serial (and wherever else that name might end up) referencing a totally unrelated MIPS SoC just seems kind of weird to me. Zev
On Thu, Feb 10, 2022 at 04:42:03PM -0800, Zev Weiss wrote: > Commit 54da3e381c2b ("serial: 8250_aspeed_vuart: use UPF_IOREMAP to > set up register mapping") fixed a bug that had, as a side-effect, > prevented the 8250_aspeed_vuart driver from enabling the VUART's > FIFOs. However, fixing that (and hence enabling the FIFOs) has in > turn revealed what appears to be a hardware bug in the ASPEED VUART in > which the host-side THRE bit doesn't get if the BMC-side receive FIFO > trigger level is set to anything but one byte. This causes problems > for polled-mode writes from the host -- for example, Linux kernel > console writes proceed at a glacial pace (less than 100 bytes per > second) because the write path waits for a 10ms timeout to expire > after every character instead of being able to continue on to the next > character upon seeing THRE asserted. (GRUB behaves similarly.) > > As a workaround, introduce a new port type for the ASPEED VUART that's > identical to PORT_16550A as it had previously been using, but with > UART_FCR_R_TRIG_00 instead to set the receive FIFO trigger level to > one byte, which (experimentally) seems to avoid the problematic THRE > behavior. Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> > Signed-off-by: Zev Weiss <zev@bewilderbeest.net> > Tested-by: Konstantin Aladyshev <aladyshev22@gmail.com> > Fixes: 54da3e381c2b ("serial: 8250_aspeed_vuart: use UPF_IOREMAP to set up register mapping") > --- > > Changes since v1 [0]: > - Added Fixes: tag > - Shifted PORT_* constant down into an unused gap > > [0] https://lore.kernel.org/all/20220209203414.23491-1-zev@bewilderbeest.net/ > > drivers/tty/serial/8250/8250_aspeed_vuart.c | 2 +- > drivers/tty/serial/8250/8250_port.c | 8 ++++++++ > include/uapi/linux/serial_core.h | 3 +++ > 3 files changed, 12 insertions(+), 1 deletion(-) > > diff --git a/drivers/tty/serial/8250/8250_aspeed_vuart.c b/drivers/tty/serial/8250/8250_aspeed_vuart.c > index 2350fb3bb5e4..c2cecc6f47db 100644 > --- a/drivers/tty/serial/8250/8250_aspeed_vuart.c > +++ b/drivers/tty/serial/8250/8250_aspeed_vuart.c > @@ -487,7 +487,7 @@ static int aspeed_vuart_probe(struct platform_device *pdev) > port.port.irq = irq_of_parse_and_map(np, 0); > port.port.handle_irq = aspeed_vuart_handle_irq; > port.port.iotype = UPIO_MEM; > - port.port.type = PORT_16550A; > + port.port.type = PORT_ASPEED_VUART; > port.port.uartclk = clk; > port.port.flags = UPF_SHARE_IRQ | UPF_BOOT_AUTOCONF | UPF_IOREMAP > | UPF_FIXED_PORT | UPF_FIXED_TYPE | UPF_NO_THRE_TEST; > diff --git a/drivers/tty/serial/8250/8250_port.c b/drivers/tty/serial/8250/8250_port.c > index 3b12bfc1ed67..973870ebff69 100644 > --- a/drivers/tty/serial/8250/8250_port.c > +++ b/drivers/tty/serial/8250/8250_port.c > @@ -307,6 +307,14 @@ static const struct serial8250_config uart_config[] = { > .rxtrig_bytes = {1, 32, 64, 112}, > .flags = UART_CAP_FIFO | UART_CAP_SLEEP, > }, > + [PORT_ASPEED_VUART] = { > + .name = "ASPEED VUART", > + .fifo_size = 16, > + .tx_loadsz = 16, > + .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00, > + .rxtrig_bytes = {1, 4, 8, 14}, > + .flags = UART_CAP_FIFO, > + }, > }; > > /* Uart divisor latch read */ > diff --git a/include/uapi/linux/serial_core.h b/include/uapi/linux/serial_core.h > index c4042dcfdc0c..8885e69178bd 100644 > --- a/include/uapi/linux/serial_core.h > +++ b/include/uapi/linux/serial_core.h > @@ -68,6 +68,9 @@ > /* NVIDIA Tegra Combined UART */ > #define PORT_TEGRA_TCU 41 > > +/* ASPEED AST2x00 virtual UART */ > +#define PORT_ASPEED_VUART 42 > + > /* Intel EG20 */ > #define PORT_PCH_8LINE 44 > #define PORT_PCH_2LINE 45 > -- > 2.35.1 >
diff --git a/drivers/tty/serial/8250/8250_aspeed_vuart.c b/drivers/tty/serial/8250/8250_aspeed_vuart.c index 2350fb3bb5e4..c2cecc6f47db 100644 --- a/drivers/tty/serial/8250/8250_aspeed_vuart.c +++ b/drivers/tty/serial/8250/8250_aspeed_vuart.c @@ -487,7 +487,7 @@ static int aspeed_vuart_probe(struct platform_device *pdev) port.port.irq = irq_of_parse_and_map(np, 0); port.port.handle_irq = aspeed_vuart_handle_irq; port.port.iotype = UPIO_MEM; - port.port.type = PORT_16550A; + port.port.type = PORT_ASPEED_VUART; port.port.uartclk = clk; port.port.flags = UPF_SHARE_IRQ | UPF_BOOT_AUTOCONF | UPF_IOREMAP | UPF_FIXED_PORT | UPF_FIXED_TYPE | UPF_NO_THRE_TEST; diff --git a/drivers/tty/serial/8250/8250_port.c b/drivers/tty/serial/8250/8250_port.c index 3b12bfc1ed67..973870ebff69 100644 --- a/drivers/tty/serial/8250/8250_port.c +++ b/drivers/tty/serial/8250/8250_port.c @@ -307,6 +307,14 @@ static const struct serial8250_config uart_config[] = { .rxtrig_bytes = {1, 32, 64, 112}, .flags = UART_CAP_FIFO | UART_CAP_SLEEP, }, + [PORT_ASPEED_VUART] = { + .name = "ASPEED VUART", + .fifo_size = 16, + .tx_loadsz = 16, + .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00, + .rxtrig_bytes = {1, 4, 8, 14}, + .flags = UART_CAP_FIFO, + }, }; /* Uart divisor latch read */ diff --git a/include/uapi/linux/serial_core.h b/include/uapi/linux/serial_core.h index c4042dcfdc0c..8885e69178bd 100644 --- a/include/uapi/linux/serial_core.h +++ b/include/uapi/linux/serial_core.h @@ -68,6 +68,9 @@ /* NVIDIA Tegra Combined UART */ #define PORT_TEGRA_TCU 41 +/* ASPEED AST2x00 virtual UART */ +#define PORT_ASPEED_VUART 42 + /* Intel EG20 */ #define PORT_PCH_8LINE 44 #define PORT_PCH_2LINE 45
Commit 54da3e381c2b ("serial: 8250_aspeed_vuart: use UPF_IOREMAP to set up register mapping") fixed a bug that had, as a side-effect, prevented the 8250_aspeed_vuart driver from enabling the VUART's FIFOs. However, fixing that (and hence enabling the FIFOs) has in turn revealed what appears to be a hardware bug in the ASPEED VUART in which the host-side THRE bit doesn't get if the BMC-side receive FIFO trigger level is set to anything but one byte. This causes problems for polled-mode writes from the host -- for example, Linux kernel console writes proceed at a glacial pace (less than 100 bytes per second) because the write path waits for a 10ms timeout to expire after every character instead of being able to continue on to the next character upon seeing THRE asserted. (GRUB behaves similarly.) As a workaround, introduce a new port type for the ASPEED VUART that's identical to PORT_16550A as it had previously been using, but with UART_FCR_R_TRIG_00 instead to set the receive FIFO trigger level to one byte, which (experimentally) seems to avoid the problematic THRE behavior. Signed-off-by: Zev Weiss <zev@bewilderbeest.net> Tested-by: Konstantin Aladyshev <aladyshev22@gmail.com> Fixes: 54da3e381c2b ("serial: 8250_aspeed_vuart: use UPF_IOREMAP to set up register mapping") --- Changes since v1 [0]: - Added Fixes: tag - Shifted PORT_* constant down into an unused gap [0] https://lore.kernel.org/all/20220209203414.23491-1-zev@bewilderbeest.net/ drivers/tty/serial/8250/8250_aspeed_vuart.c | 2 +- drivers/tty/serial/8250/8250_port.c | 8 ++++++++ include/uapi/linux/serial_core.h | 3 +++ 3 files changed, 12 insertions(+), 1 deletion(-)