| Message ID | 20220128142056.359900-1-angelogioacchino.delregno@collabora.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | soc: mediatek: mt8192-mmsys: Fix dither to dsi0 path's input sel | expand |
On Fri, Jan 28, 2022 at 03:20:56PM +0100, AngeloGioacchino Del Regno wrote: > In commit d687e056a18f ("soc: mediatek: mmsys: Add mt8192 mmsys routing table"), > the mmsys routing table for mt8192 was introduced but the input selector > for DITHER->DSI0 has no value assigned to it. > > This means that we are clearing bit 0 instead of setting it, blocking > communication between these two blocks; due to that, any display that > is connected to DSI0 will not work, as no data will go through. > The effect of that issue is that, during bootup, the DRM will block for > some time, while atomically waiting for a vblank that never happens; > later, the situation doesn't get better, leaving the display in a > non-functional state. > > To fix this issue, fix the route entry in the table by assigning the > dither input selector to MT8192_DISP_DSI0_SEL_IN. > > Fixes: d687e056a18f ("soc: mediatek: mmsys: Add mt8192 mmsys routing table") > Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> > --- > drivers/soc/mediatek/mt8192-mmsys.h | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/soc/mediatek/mt8192-mmsys.h b/drivers/soc/mediatek/mt8192-mmsys.h > index 6f0a57044a7b..6aae0b12b6ff 100644 > --- a/drivers/soc/mediatek/mt8192-mmsys.h > +++ b/drivers/soc/mediatek/mt8192-mmsys.h > @@ -53,7 +53,8 @@ static const struct mtk_mmsys_routes mmsys_mt8192_routing_table[] = { > MT8192_AAL0_SEL_IN_CCORR0 > }, { > DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0, > - MT8192_DISP_DSI0_SEL_IN, MT8192_DSI0_SEL_IN_DITHER0 > + MT8192_DISP_DSI0_SEL_IN, MT8192_DSI0_SEL_IN_DITHER0, > + MT8192_DSI0_SEL_IN_DITHER0 > }, { > DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0, > MT8192_DISP_RDMA0_SOUT_SEL, MT8192_RDMA0_SOUT_COLOR0, > -- > 2.33.1 > > > -- > To unsubscribe, send mail to kernel-unsubscribe@lists.collabora.co.uk.
> In commit d687e056a18f ("soc: mediatek: mmsys: Add mt8192 mmsys routing table"), > the mmsys routing table for mt8192 was introduced but the input selector > for DITHER->DSI0 has no value assigned to it. > > This means that we are clearing bit 0 instead of setting it, blocking > communication between these two blocks; due to that, any display that > is connected to DSI0 will not work, as no data will go through. > The effect of that issue is that, during bootup, the DRM will block for > some time, while atomically waiting for a vblank that never happens; > later, the situation doesn't get better, leaving the display in a > non-functional state. > > To fix this issue, fix the route entry in the table by assigning the > dither input selector to MT8192_DISP_DSI0_SEL_IN. > > Fixes: d687e056a18f ("soc: mediatek: mmsys: Add mt8192 mmsys routing table") > Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> > --- > drivers/soc/mediatek/mt8192-mmsys.h | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/soc/mediatek/mt8192-mmsys.h b/drivers/soc/mediatek/mt8192-mmsys.h > index 6f0a57044a7b..6aae0b12b6ff 100644 > --- a/drivers/soc/mediatek/mt8192-mmsys.h > +++ b/drivers/soc/mediatek/mt8192-mmsys.h > @@ -53,7 +53,8 @@ static const struct mtk_mmsys_routes mmsys_mt8192_routing_table[] = { > MT8192_AAL0_SEL_IN_CCORR0 > }, { > DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0, > - MT8192_DISP_DSI0_SEL_IN, MT8192_DSI0_SEL_IN_DITHER0 > + MT8192_DISP_DSI0_SEL_IN, MT8192_DSI0_SEL_IN_DITHER0, > + MT8192_DSI0_SEL_IN_DITHER0 > }, { > DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0, > MT8192_DISP_RDMA0_SOUT_SEL, MT8192_RDMA0_SOUT_COLOR0, Tested-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
On 28/01/2022 15:20, AngeloGioacchino Del Regno wrote: > In commit d687e056a18f ("soc: mediatek: mmsys: Add mt8192 mmsys routing table"), > the mmsys routing table for mt8192 was introduced but the input selector > for DITHER->DSI0 has no value assigned to it. > > This means that we are clearing bit 0 instead of setting it, blocking > communication between these two blocks; due to that, any display that > is connected to DSI0 will not work, as no data will go through. > The effect of that issue is that, during bootup, the DRM will block for > some time, while atomically waiting for a vblank that never happens; > later, the situation doesn't get better, leaving the display in a > non-functional state. > > To fix this issue, fix the route entry in the table by assigning the > dither input selector to MT8192_DISP_DSI0_SEL_IN. > > Fixes: d687e056a18f ("soc: mediatek: mmsys: Add mt8192 mmsys routing table") > Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Applied, thanks! > --- > drivers/soc/mediatek/mt8192-mmsys.h | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/soc/mediatek/mt8192-mmsys.h b/drivers/soc/mediatek/mt8192-mmsys.h > index 6f0a57044a7b..6aae0b12b6ff 100644 > --- a/drivers/soc/mediatek/mt8192-mmsys.h > +++ b/drivers/soc/mediatek/mt8192-mmsys.h > @@ -53,7 +53,8 @@ static const struct mtk_mmsys_routes mmsys_mt8192_routing_table[] = { > MT8192_AAL0_SEL_IN_CCORR0 > }, { > DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0, > - MT8192_DISP_DSI0_SEL_IN, MT8192_DSI0_SEL_IN_DITHER0 > + MT8192_DISP_DSI0_SEL_IN, MT8192_DSI0_SEL_IN_DITHER0, > + MT8192_DSI0_SEL_IN_DITHER0 > }, { > DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0, > MT8192_DISP_RDMA0_SOUT_SEL, MT8192_RDMA0_SOUT_COLOR0,
diff --git a/drivers/soc/mediatek/mt8192-mmsys.h b/drivers/soc/mediatek/mt8192-mmsys.h index 6f0a57044a7b..6aae0b12b6ff 100644 --- a/drivers/soc/mediatek/mt8192-mmsys.h +++ b/drivers/soc/mediatek/mt8192-mmsys.h @@ -53,7 +53,8 @@ static const struct mtk_mmsys_routes mmsys_mt8192_routing_table[] = { MT8192_AAL0_SEL_IN_CCORR0 }, { DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0, - MT8192_DISP_DSI0_SEL_IN, MT8192_DSI0_SEL_IN_DITHER0 + MT8192_DISP_DSI0_SEL_IN, MT8192_DSI0_SEL_IN_DITHER0, + MT8192_DSI0_SEL_IN_DITHER0 }, { DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0, MT8192_DISP_RDMA0_SOUT_SEL, MT8192_RDMA0_SOUT_COLOR0,
In commit d687e056a18f ("soc: mediatek: mmsys: Add mt8192 mmsys routing table"), the mmsys routing table for mt8192 was introduced but the input selector for DITHER->DSI0 has no value assigned to it. This means that we are clearing bit 0 instead of setting it, blocking communication between these two blocks; due to that, any display that is connected to DSI0 will not work, as no data will go through. The effect of that issue is that, during bootup, the DRM will block for some time, while atomically waiting for a vblank that never happens; later, the situation doesn't get better, leaving the display in a non-functional state. To fix this issue, fix the route entry in the table by assigning the dither input selector to MT8192_DISP_DSI0_SEL_IN. Fixes: d687e056a18f ("soc: mediatek: mmsys: Add mt8192 mmsys routing table") Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> --- drivers/soc/mediatek/mt8192-mmsys.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)