| Message ID | 20220211202728.6146-8-alyssa.rosenzweig@collabora.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/panfrost: Initial Valhall support | expand |
On 11/02/2022 20:27, alyssa.rosenzweig@collabora.com wrote: > From: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> > > L2_MMU_CONFIG is an implementation-defined register. Different Mali GPUs > define slightly different MAX_READS and MAX_WRITES fields, which > throttle outstanding reads and writes when set to non-zero values. When > left as zero, reads and writes are not throttled. > > Both kbase and panfrost always zero these registers. Per discussion with > Steven Price, there are two reasons these quirks may be used: > > 1. Simulating slower memory subsystems. This use case is only of > interest to system-on-chip designers; it is not relevant to mainline. > > 2. Working around broken memory subsystems. Hopefully we never see this > case in mainline. If we do, we'll need to set this register based on > an SoC-compatible, rather than generally matching on the GPU model. > > To the best of our knowledge, these fields are zero at reset, so the > write is not necessary. Let's remove the write to aid porting to new > Mali GPUs, which have different layouts for the L2_MMU_CONFIG register. > > Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> > Suggested-by: Steven Price <steven.price@arm.com> Reviewed-by: Steven Price <steven.price@arm.com> > --- > drivers/gpu/drm/panfrost/panfrost_gpu.c | 12 ------------ > 1 file changed, 12 deletions(-) > > diff --git a/drivers/gpu/drm/panfrost/panfrost_gpu.c b/drivers/gpu/drm/panfrost/panfrost_gpu.c > index 1c1e2017aa80..73e5774f01c1 100644 > --- a/drivers/gpu/drm/panfrost/panfrost_gpu.c > +++ b/drivers/gpu/drm/panfrost/panfrost_gpu.c > @@ -127,18 +127,6 @@ static void panfrost_gpu_init_quirks(struct panfrost_device *pfdev) > gpu_write(pfdev, GPU_TILER_CONFIG, quirks); > > > - quirks = gpu_read(pfdev, GPU_L2_MMU_CONFIG); > - > - /* Limit read & write ID width for AXI */ > - if (panfrost_has_hw_feature(pfdev, HW_FEATURE_3BIT_EXT_RW_L2_MMU_CONFIG)) > - quirks &= ~(L2_MMU_CONFIG_3BIT_LIMIT_EXTERNAL_READS | > - L2_MMU_CONFIG_3BIT_LIMIT_EXTERNAL_WRITES); > - else > - quirks &= ~(L2_MMU_CONFIG_LIMIT_EXTERNAL_READS | > - L2_MMU_CONFIG_LIMIT_EXTERNAL_WRITES); > - > - gpu_write(pfdev, GPU_L2_MMU_CONFIG, quirks); > - > quirks = 0; > if ((panfrost_model_eq(pfdev, 0x860) || panfrost_model_eq(pfdev, 0x880)) && > pfdev->features.revision >= 0x2000)
diff --git a/drivers/gpu/drm/panfrost/panfrost_gpu.c b/drivers/gpu/drm/panfrost/panfrost_gpu.c index 1c1e2017aa80..73e5774f01c1 100644 --- a/drivers/gpu/drm/panfrost/panfrost_gpu.c +++ b/drivers/gpu/drm/panfrost/panfrost_gpu.c @@ -127,18 +127,6 @@ static void panfrost_gpu_init_quirks(struct panfrost_device *pfdev) gpu_write(pfdev, GPU_TILER_CONFIG, quirks); - quirks = gpu_read(pfdev, GPU_L2_MMU_CONFIG); - - /* Limit read & write ID width for AXI */ - if (panfrost_has_hw_feature(pfdev, HW_FEATURE_3BIT_EXT_RW_L2_MMU_CONFIG)) - quirks &= ~(L2_MMU_CONFIG_3BIT_LIMIT_EXTERNAL_READS | - L2_MMU_CONFIG_3BIT_LIMIT_EXTERNAL_WRITES); - else - quirks &= ~(L2_MMU_CONFIG_LIMIT_EXTERNAL_READS | - L2_MMU_CONFIG_LIMIT_EXTERNAL_WRITES); - - gpu_write(pfdev, GPU_L2_MMU_CONFIG, quirks); - quirks = 0; if ((panfrost_model_eq(pfdev, 0x860) || panfrost_model_eq(pfdev, 0x880)) && pfdev->features.revision >= 0x2000)