| Message ID | 20220118092117.10089-1-liudongdong3@huawei.com (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | 3dc8a1f6f64481a8a5a669633e880f26dae0d752 |
| Delegated to: | Bjorn Helgaas |
| Headers | show |
| Series | PCI: Support BAR sizes up to 8TB | expand |
Hi Gentle ping... On 2022/1/18 17:21, Dongdong Liu wrote: > Current kernel reports disabling BAR if device with a 4TB BAR as it > only supports BAR size to 128GB. > > pci 0000:01:00.0: disabling BAR 4: > [mem 0x00000000-0x3ffffffffff 64bit pref] (bad alignment 0x40000000000) > > Increase the maximum BAR size from 128GB to 8TB for future expansion. > > Signed-off-by: Dongdong Liu <liudongdong3@huawei.com> > --- > drivers/pci/setup-bus.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c > index 547396ec50b5..a7893bf2f580 100644 > --- a/drivers/pci/setup-bus.c > +++ b/drivers/pci/setup-bus.c > @@ -994,7 +994,7 @@ static int pbus_size_mem(struct pci_bus *bus, unsigned long mask, > { > struct pci_dev *dev; > resource_size_t min_align, align, size, size0, size1; > - resource_size_t aligns[18]; /* Alignments from 1MB to 128GB */ > + resource_size_t aligns[24]; /* Alignments from 1MB to 8TB */ > int order, max_order; > struct resource *b_res = find_bus_resource_of_type(bus, > mask | IORESOURCE_PREFETCH, type); >
Hi Bjorn Could you help to review this patch, I hope this patch can be applied for 5.18. Thanks， Dongdong On 2022/1/18 17:21, Dongdong Liu wrote: > Current kernel reports disabling BAR if device with a 4TB BAR as it > only supports BAR size to 128GB. > > pci 0000:01:00.0: disabling BAR 4: > [mem 0x00000000-0x3ffffffffff 64bit pref] (bad alignment 0x40000000000) > > Increase the maximum BAR size from 128GB to 8TB for future expansion. > > Signed-off-by: Dongdong Liu <liudongdong3@huawei.com> > --- > drivers/pci/setup-bus.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c > index 547396ec50b5..a7893bf2f580 100644 > --- a/drivers/pci/setup-bus.c > +++ b/drivers/pci/setup-bus.c > @@ -994,7 +994,7 @@ static int pbus_size_mem(struct pci_bus *bus, unsigned long mask, > { > struct pci_dev *dev; > resource_size_t min_align, align, size, size0, size1; > - resource_size_t aligns[18]; /* Alignments from 1MB to 128GB */ > + resource_size_t aligns[24]; /* Alignments from 1MB to 8TB */ > int order, max_order; > struct resource *b_res = find_bus_resource_of_type(bus, > mask | IORESOURCE_PREFETCH, type); >
On Tue, Jan 18, 2022 at 05:21:17PM +0800, Dongdong Liu wrote: > Current kernel reports disabling BAR if device with a 4TB BAR as it > only supports BAR size to 128GB. > > pci 0000:01:00.0: disabling BAR 4: > [mem 0x00000000-0x3ffffffffff 64bit pref] (bad alignment 0x40000000000) > > Increase the maximum BAR size from 128GB to 8TB for future expansion. > > Signed-off-by: Dongdong Liu <liudongdong3@huawei.com> Applied to pci/enumeration for v5.18, thanks! > --- > drivers/pci/setup-bus.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c > index 547396ec50b5..a7893bf2f580 100644 > --- a/drivers/pci/setup-bus.c > +++ b/drivers/pci/setup-bus.c > @@ -994,7 +994,7 @@ static int pbus_size_mem(struct pci_bus *bus, unsigned long mask, > { > struct pci_dev *dev; > resource_size_t min_align, align, size, size0, size1; > - resource_size_t aligns[18]; /* Alignments from 1MB to 128GB */ > + resource_size_t aligns[24]; /* Alignments from 1MB to 8TB */ > int order, max_order; > struct resource *b_res = find_bus_resource_of_type(bus, > mask | IORESOURCE_PREFETCH, type); > -- > 2.33.0 >
diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c index 547396ec50b5..a7893bf2f580 100644 --- a/drivers/pci/setup-bus.c +++ b/drivers/pci/setup-bus.c @@ -994,7 +994,7 @@ static int pbus_size_mem(struct pci_bus *bus, unsigned long mask, { struct pci_dev *dev; resource_size_t min_align, align, size, size0, size1; - resource_size_t aligns[18]; /* Alignments from 1MB to 128GB */ + resource_size_t aligns[24]; /* Alignments from 1MB to 8TB */ int order, max_order; struct resource *b_res = find_bus_resource_of_type(bus, mask | IORESOURCE_PREFETCH, type);
Current kernel reports disabling BAR if device with a 4TB BAR as it only supports BAR size to 128GB. pci 0000:01:00.0: disabling BAR 4: [mem 0x00000000-0x3ffffffffff 64bit pref] (bad alignment 0x40000000000) Increase the maximum BAR size from 128GB to 8TB for future expansion. Signed-off-by: Dongdong Liu <liudongdong3@huawei.com> --- drivers/pci/setup-bus.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)