| Message ID | 20220202172540.2458-1-tdas@codeaurora.org (mailing list archive) |
|---|---|
| State | Changes Requested, archived |
| Headers | show |
| Series | [v2,1/2] clk: qcom: clk-rcg2: Update logic to calculate D value for RCG | expand |
Quoting Taniya Das (2022-02-02 09:25:39) > The current implementation does not check for D value is within > the accepted range for a given M & N value. Update the logic to > calculate the final D value based on the range. Is this fixing any SoC that's supported now? Or is it future work? This is important to know if this needs to be merged this week or next merge window. > > Fixes: 99cbd064b059f ("clk: qcom: Support display RCG clocks") > Signed-off-by: Taniya Das <tdas@codeaurora.org> > --- > * Split the patch and update the Fixes tag. > > drivers/clk/qcom/clk-rcg2.c | 14 ++++++++++++-- > 1 file changed, 12 insertions(+), 2 deletions(-) > > diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c > index e1b1b426fae4..34251ec98def 100644 > --- a/drivers/clk/qcom/clk-rcg2.c > +++ b/drivers/clk/qcom/clk-rcg2.c > @@ -264,7 +264,7 @@ static int clk_rcg2_determine_floor_rate(struct clk_hw *hw, > > static int __clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f) > { > - u32 cfg, mask; > + u32 cfg, mask, d_val, not2d_val; > struct clk_hw *hw = &rcg->clkr.hw; > int ret, index = qcom_find_src_index(hw, rcg->parent_map, f->src); > > @@ -283,8 +283,18 @@ static int __clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f) > if (ret) > return ret; > > + /* Calculate 2d value */ > + d_val = f->n; > + > + if (d_val > ((f->n - f->m) * 2)) Please make another local variable for (f->n - f->m) * 2 u32 n_minus_m; ... n_minus_m = f->n - f->m; n_minus_m *= 2; d_val = clamp(d_val, f->m, n_minus_m); not2d_val = ~d_val & mask; would be better than if else logic because the types are all verified to be compatible. > + d_val = (f->n - f->m) * 2; > + else if (d_val < f->m) > + d_val = f->m; > + > + not2d_val = ~d_val & mask; > + > ret = regmap_update_bits(rcg->clkr.regmap, > - RCG_D_OFFSET(rcg), mask, ~f->n); > + RCG_D_OFFSET(rcg), mask, not2d_val); > if (ret) > return ret;
diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c index e1b1b426fae4..34251ec98def 100644 --- a/drivers/clk/qcom/clk-rcg2.c +++ b/drivers/clk/qcom/clk-rcg2.c @@ -264,7 +264,7 @@ static int clk_rcg2_determine_floor_rate(struct clk_hw *hw, static int __clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f) { - u32 cfg, mask; + u32 cfg, mask, d_val, not2d_val; struct clk_hw *hw = &rcg->clkr.hw; int ret, index = qcom_find_src_index(hw, rcg->parent_map, f->src); @@ -283,8 +283,18 @@ static int __clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f) if (ret) return ret; + /* Calculate 2d value */ + d_val = f->n; + + if (d_val > ((f->n - f->m) * 2)) + d_val = (f->n - f->m) * 2; + else if (d_val < f->m) + d_val = f->m; + + not2d_val = ~d_val & mask; + ret = regmap_update_bits(rcg->clkr.regmap, - RCG_D_OFFSET(rcg), mask, ~f->n); + RCG_D_OFFSET(rcg), mask, not2d_val); if (ret) return ret; }
The current implementation does not check for D value is within the accepted range for a given M & N value. Update the logic to calculate the final D value based on the range. Fixes: 99cbd064b059f ("clk: qcom: Support display RCG clocks") Signed-off-by: Taniya Das <tdas@codeaurora.org> --- * Split the patch and update the Fixes tag. drivers/clk/qcom/clk-rcg2.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) -- Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member of the Code Aurora Forum, hosted by the Linux Foundation.