| Message ID | 20220219064210.3145381-5-shorne@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | OpenRISC Device Tree Generation | expand |
On Sat, 19 Feb 2022 at 06:42, Stafford Horne <shorne@gmail.com> wrote: > > Now that we no longer have a limit of 2 CPUs due to fixing the > IRQ routing issues we can increase the max. Here we increase > the limit to 4, we could go higher, but currently OMPIC has a > limit of 4, so we align with that. > > Signed-off-by: Stafford Horne <shorne@gmail.com> > --- > hw/openrisc/openrisc_sim.c | 8 +++++--- > 1 file changed, 5 insertions(+), 3 deletions(-) > Reviewed-by: Peter Maydell <peter.maydell@linaro.org> thanks -- PMM
On 19/2/22 07:42, Stafford Horne wrote: > Now that we no longer have a limit of 2 CPUs due to fixing the > IRQ routing issues we can increase the max. Here we increase > the limit to 4, we could go higher, but currently OMPIC has a > limit of 4, so we align with that. > > Signed-off-by: Stafford Horne <shorne@gmail.com> > --- > hw/openrisc/openrisc_sim.c | 8 +++++--- > 1 file changed, 5 insertions(+), 3 deletions(-) Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
On Sun, Feb 20, 2022 at 09:07:17PM +0100, Philippe Mathieu-Daudé wrote: > On 19/2/22 07:42, Stafford Horne wrote: > > Now that we no longer have a limit of 2 CPUs due to fixing the > > IRQ routing issues we can increase the max. Here we increase > > the limit to 4, we could go higher, but currently OMPIC has a > > limit of 4, so we align with that. > > > > Signed-off-by: Stafford Horne <shorne@gmail.com> > > --- > > hw/openrisc/openrisc_sim.c | 8 +++++--- > > 1 file changed, 5 insertions(+), 3 deletions(-) > > Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Thank you. -Stafford
diff --git a/hw/openrisc/openrisc_sim.c b/hw/openrisc/openrisc_sim.c index 5bfbac00f8..8cfb92bec6 100644 --- a/hw/openrisc/openrisc_sim.c +++ b/hw/openrisc/openrisc_sim.c @@ -37,6 +37,8 @@ #define KERNEL_LOAD_ADDR 0x100 +#define OR1KSIM_CPUS_MAX 4 + #define TYPE_OR1KSIM_MACHINE MACHINE_TYPE_NAME("or1k-sim") #define OR1KSIM_MACHINE(obj) \ OBJECT_CHECK(Or1ksimState, (obj), TYPE_OR1KSIM_MACHINE) @@ -197,12 +199,12 @@ static void openrisc_sim_init(MachineState *machine) { ram_addr_t ram_size = machine->ram_size; const char *kernel_filename = machine->kernel_filename; - OpenRISCCPU *cpus[2] = {}; + OpenRISCCPU *cpus[OR1KSIM_CPUS_MAX] = {}; MemoryRegion *ram; int n; unsigned int smp_cpus = machine->smp.cpus; - assert(smp_cpus >= 1 && smp_cpus <= 2); + assert(smp_cpus >= 1 && smp_cpus <= OR1KSIM_CPUS_MAX); for (n = 0; n < smp_cpus; n++) { cpus[n] = OPENRISC_CPU(cpu_create(machine->cpu_type)); if (cpus[n] == NULL) { @@ -243,7 +245,7 @@ static void openrisc_sim_machine_init(ObjectClass *oc, void *data) mc->desc = "or1k simulation"; mc->init = openrisc_sim_init; - mc->max_cpus = 2; + mc->max_cpus = OR1KSIM_CPUS_MAX; mc->is_default = true; mc->default_cpu_type = OPENRISC_CPU_TYPE_NAME("or1200"); }
Now that we no longer have a limit of 2 CPUs due to fixing the IRQ routing issues we can increase the max. Here we increase the limit to 4, we could go higher, but currently OMPIC has a limit of 4, so we align with that. Signed-off-by: Stafford Horne <shorne@gmail.com> --- hw/openrisc/openrisc_sim.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-)