| Message ID | 20220222141424.35165-1-jose.souza@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v2] drm/i915/tgl: Simply subplatform detection | expand |
On 22/02/2022 14:14, José Roberto de Souza wrote: > In the past we had a need to differentiate TGL U and TGL Y, there > was a different voltage swing table for each subplatform and some PCI > ids of this subplatforms are shared but it turned out that it was a > specification mistake and the voltage swing table was indeed the same > but we went ahead with that patch because we needed to differentiate > TGL U and Y from TGL H and by that time TGL H was embargoed so that > was the perfect way to land it upstream. > > Now the embargo for TGL H is long past and now we even have > INTEL_TGL_12_GT1_IDS with all TGL H ids, so we can drop this PCI root > check and only rely in the PCI ids to differentiate TGL U and Y from > TGL H that actually has code differences. > > Besides the simplification this will fix issues in virtualization > environments where the PCI root is virtualized and don't have the same > id as actual hardware. > > v2: > - add and set INTEL_SUBPLATFORM_UY LGTM, thanks for the tweak! Looks mechanical enough so: Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Regards, Tvrtko > Cc: Fred Gao <fred.gao@intel.com> > Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com> > --- > .../drm/i915/display/intel_ddi_buf_trans.c | 2 +- > drivers/gpu/drm/i915/i915_drv.h | 11 +++----- > drivers/gpu/drm/i915/i915_reg.h | 6 ----- > drivers/gpu/drm/i915/intel_device_info.c | 26 +++++-------------- > drivers/gpu/drm/i915/intel_device_info.h | 3 +++ > drivers/gpu/drm/i915/intel_step.c | 2 +- > 6 files changed, 16 insertions(+), 34 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c > index 0c32210bf5031..934a9f9e7dabb 100644 > --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c > +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c > @@ -1321,7 +1321,7 @@ tgl_get_combo_buf_trans_dp(struct intel_encoder *encoder, > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > > if (crtc_state->port_clock > 270000) { > - if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv)) { > + if (IS_TGL_UY(dev_priv)) { > return intel_get_buf_trans(&tgl_uy_combo_phy_trans_dp_hbr2, > n_entries); > } else { > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index 1c2f4ae4ebf98..51417e9b740f4 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -1147,11 +1147,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, > #define IS_ICL_WITH_PORT_F(dev_priv) \ > IS_SUBPLATFORM(dev_priv, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF) > > -#define IS_TGL_U(dev_priv) \ > - IS_SUBPLATFORM(dev_priv, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_ULT) > - > -#define IS_TGL_Y(dev_priv) \ > - IS_SUBPLATFORM(dev_priv, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_ULX) > +#define IS_TGL_UY(dev_priv) \ > + IS_SUBPLATFORM(dev_priv, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_UY) > > #define IS_SKL_GRAPHICS_STEP(p, since, until) (IS_SKYLAKE(p) && IS_GRAPHICS_STEP(p, since, until)) > > @@ -1170,11 +1167,11 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, > IS_DISPLAY_STEP(__i915, since, until)) > > #define IS_TGL_UY_GRAPHICS_STEP(__i915, since, until) \ > - ((IS_TGL_U(__i915) || IS_TGL_Y(__i915)) && \ > + (IS_TGL_UY(__i915) && \ > IS_GRAPHICS_STEP(__i915, since, until)) > > #define IS_TGL_GRAPHICS_STEP(__i915, since, until) \ > - (IS_TIGERLAKE(__i915) && !(IS_TGL_U(__i915) || IS_TGL_Y(__i915)) && \ > + (IS_TIGERLAKE(__i915) && !IS_TGL_UY(__i915)) && \ > IS_GRAPHICS_STEP(__i915, since, until)) > > #define IS_RKL_DISPLAY_STEP(p, since, until) \ > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 2b8a3086ed35a..30aa1d99f2244 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -8823,12 +8823,6 @@ enum skl_power_gate { > #define DSB_ENABLE (1 << 31) > #define DSB_STATUS (1 << 0) > > -#define TGL_ROOT_DEVICE_ID 0x9A00 > -#define TGL_ROOT_DEVICE_MASK 0xFF00 > -#define TGL_ROOT_DEVICE_SKU_MASK 0xF > -#define TGL_ROOT_DEVICE_SKU_ULX 0x2 > -#define TGL_ROOT_DEVICE_SKU_ULT 0x4 > - > #define CLKREQ_POLICY _MMIO(0x101038) > #define CLKREQ_POLICY_MEM_UP_OVRD REG_BIT(1) > > diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c > index ae13bc3c7970e..d03de76147912 100644 > --- a/drivers/gpu/drm/i915/intel_device_info.c > +++ b/drivers/gpu/drm/i915/intel_device_info.c > @@ -170,6 +170,10 @@ static const u16 subplatform_portf_ids[] = { > INTEL_ICL_PORT_F_IDS(0), > }; > > +static const u16 subplatform_uy_ids[] = { > + INTEL_TGL_12_GT2_IDS(0), > +}; > + > static const u16 subplatform_n_ids[] = { > INTEL_ADLN_IDS(0), > }; > @@ -226,6 +230,9 @@ void intel_device_info_subplatform_init(struct drm_i915_private *i915) > } else if (find_devid(devid, subplatform_portf_ids, > ARRAY_SIZE(subplatform_portf_ids))) { > mask = BIT(INTEL_SUBPLATFORM_PORTF); > + } else if (find_devid(devid, subplatform_uy_ids, > + ARRAY_SIZE(subplatform_uy_ids))) { > + mask = BIT(INTEL_SUBPLATFORM_UY); > } else if (find_devid(devid, subplatform_n_ids, > ARRAY_SIZE(subplatform_n_ids))) { > mask = BIT(INTEL_SUBPLATFORM_N); > @@ -243,25 +250,6 @@ void intel_device_info_subplatform_init(struct drm_i915_private *i915) > mask = BIT(INTEL_SUBPLATFORM_G12); > } > > - if (IS_TIGERLAKE(i915)) { > - struct pci_dev *root, *pdev = to_pci_dev(i915->drm.dev); > - > - root = list_first_entry(&pdev->bus->devices, typeof(*root), bus_list); > - > - drm_WARN_ON(&i915->drm, mask); > - drm_WARN_ON(&i915->drm, (root->device & TGL_ROOT_DEVICE_MASK) != > - TGL_ROOT_DEVICE_ID); > - > - switch (root->device & TGL_ROOT_DEVICE_SKU_MASK) { > - case TGL_ROOT_DEVICE_SKU_ULX: > - mask = BIT(INTEL_SUBPLATFORM_ULX); > - break; > - case TGL_ROOT_DEVICE_SKU_ULT: > - mask = BIT(INTEL_SUBPLATFORM_ULT); > - break; > - } > - } > - > GEM_BUG_ON(mask & ~INTEL_SUBPLATFORM_MASK); > > RUNTIME_INFO(i915)->platform_mask[pi] |= mask; > diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h > index 2508a47fb3f5e..291215d9da282 100644 > --- a/drivers/gpu/drm/i915/intel_device_info.h > +++ b/drivers/gpu/drm/i915/intel_device_info.h > @@ -106,6 +106,9 @@ enum intel_platform { > /* ICL */ > #define INTEL_SUBPLATFORM_PORTF (0) > > +/* TGL */ > +#define INTEL_SUBPLATFORM_UY (0) > + > /* DG2 */ > #define INTEL_SUBPLATFORM_G10 0 > #define INTEL_SUBPLATFORM_G11 1 > diff --git a/drivers/gpu/drm/i915/intel_step.c b/drivers/gpu/drm/i915/intel_step.c > index ac1a796b28084..4fd69ecd14811 100644 > --- a/drivers/gpu/drm/i915/intel_step.c > +++ b/drivers/gpu/drm/i915/intel_step.c > @@ -165,7 +165,7 @@ void intel_step_init(struct drm_i915_private *i915) > } else if (IS_ROCKETLAKE(i915)) { > revids = rkl_revids; > size = ARRAY_SIZE(rkl_revids); > - } else if (IS_TGL_U(i915) || IS_TGL_Y(i915)) { > + } else if (IS_TGL_UY(i915)) { > revids = tgl_uy_revids; > size = ARRAY_SIZE(tgl_uy_revids); > } else if (IS_TIGERLAKE(i915)) {
On 2022.02.22 14:21:33 +0000, Tvrtko Ursulin wrote: > > On 22/02/2022 14:14, Jos?? Roberto de Souza wrote: > > In the past we had a need to differentiate TGL U and TGL Y, there > > was a different voltage swing table for each subplatform and some PCI > > ids of this subplatforms are shared but it turned out that it was a > > specification mistake and the voltage swing table was indeed the same > > but we went ahead with that patch because we needed to differentiate > > TGL U and Y from TGL H and by that time TGL H was embargoed so that > > was the perfect way to land it upstream. > > > > Now the embargo for TGL H is long past and now we even have > > INTEL_TGL_12_GT1_IDS with all TGL H ids, so we can drop this PCI root > > check and only rely in the PCI ids to differentiate TGL U and Y from > > TGL H that actually has code differences. > > > > Besides the simplification this will fix issues in virtualization > > environments where the PCI root is virtualized and don't have the same > > id as actual hardware. > > > > v2: > > - add and set INTEL_SUBPLATFORM_UY > > LGTM, thanks for the tweak! > > Looks mechanical enough so: > > Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> > Add Yu, who has been testing this under GPU passthrough case as well, which now release our effort for root pci device info passthrough issue. Thanks! > > > Cc: Fred Gao <fred.gao@intel.com> > > Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> > > Signed-off-by: Jos?? Roberto de Souza <jose.souza@intel.com> > > --- > > .../drm/i915/display/intel_ddi_buf_trans.c | 2 +- > > drivers/gpu/drm/i915/i915_drv.h | 11 +++----- > > drivers/gpu/drm/i915/i915_reg.h | 6 ----- > > drivers/gpu/drm/i915/intel_device_info.c | 26 +++++-------------- > > drivers/gpu/drm/i915/intel_device_info.h | 3 +++ > > drivers/gpu/drm/i915/intel_step.c | 2 +- > > 6 files changed, 16 insertions(+), 34 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c > > index 0c32210bf5031..934a9f9e7dabb 100644 > > --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c > > +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c > > @@ -1321,7 +1321,7 @@ tgl_get_combo_buf_trans_dp(struct intel_encoder *encoder, > > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > > if (crtc_state->port_clock > 270000) { > > - if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv)) { > > + if (IS_TGL_UY(dev_priv)) { > > return intel_get_buf_trans(&tgl_uy_combo_phy_trans_dp_hbr2, > > n_entries); > > } else { > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > > index 1c2f4ae4ebf98..51417e9b740f4 100644 > > --- a/drivers/gpu/drm/i915/i915_drv.h > > +++ b/drivers/gpu/drm/i915/i915_drv.h > > @@ -1147,11 +1147,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, > > #define IS_ICL_WITH_PORT_F(dev_priv) \ > > IS_SUBPLATFORM(dev_priv, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF) > > -#define IS_TGL_U(dev_priv) \ > > - IS_SUBPLATFORM(dev_priv, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_ULT) > > - > > -#define IS_TGL_Y(dev_priv) \ > > - IS_SUBPLATFORM(dev_priv, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_ULX) > > +#define IS_TGL_UY(dev_priv) \ > > + IS_SUBPLATFORM(dev_priv, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_UY) > > #define IS_SKL_GRAPHICS_STEP(p, since, until) (IS_SKYLAKE(p) && IS_GRAPHICS_STEP(p, since, until)) > > @@ -1170,11 +1167,11 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, > > IS_DISPLAY_STEP(__i915, since, until)) > > #define IS_TGL_UY_GRAPHICS_STEP(__i915, since, until) \ > > - ((IS_TGL_U(__i915) || IS_TGL_Y(__i915)) && \ > > + (IS_TGL_UY(__i915) && \ > > IS_GRAPHICS_STEP(__i915, since, until)) > > #define IS_TGL_GRAPHICS_STEP(__i915, since, until) \ > > - (IS_TIGERLAKE(__i915) && !(IS_TGL_U(__i915) || IS_TGL_Y(__i915)) && \ > > + (IS_TIGERLAKE(__i915) && !IS_TGL_UY(__i915)) && \ > > IS_GRAPHICS_STEP(__i915, since, until)) > > #define IS_RKL_DISPLAY_STEP(p, since, until) \ > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > > index 2b8a3086ed35a..30aa1d99f2244 100644 > > --- a/drivers/gpu/drm/i915/i915_reg.h > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > @@ -8823,12 +8823,6 @@ enum skl_power_gate { > > #define DSB_ENABLE (1 << 31) > > #define DSB_STATUS (1 << 0) > > -#define TGL_ROOT_DEVICE_ID 0x9A00 > > -#define TGL_ROOT_DEVICE_MASK 0xFF00 > > -#define TGL_ROOT_DEVICE_SKU_MASK 0xF > > -#define TGL_ROOT_DEVICE_SKU_ULX 0x2 > > -#define TGL_ROOT_DEVICE_SKU_ULT 0x4 > > - > > #define CLKREQ_POLICY _MMIO(0x101038) > > #define CLKREQ_POLICY_MEM_UP_OVRD REG_BIT(1) > > diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c > > index ae13bc3c7970e..d03de76147912 100644 > > --- a/drivers/gpu/drm/i915/intel_device_info.c > > +++ b/drivers/gpu/drm/i915/intel_device_info.c > > @@ -170,6 +170,10 @@ static const u16 subplatform_portf_ids[] = { > > INTEL_ICL_PORT_F_IDS(0), > > }; > > +static const u16 subplatform_uy_ids[] = { > > + INTEL_TGL_12_GT2_IDS(0), > > +}; > > + > > static const u16 subplatform_n_ids[] = { > > INTEL_ADLN_IDS(0), > > }; > > @@ -226,6 +230,9 @@ void intel_device_info_subplatform_init(struct drm_i915_private *i915) > > } else if (find_devid(devid, subplatform_portf_ids, > > ARRAY_SIZE(subplatform_portf_ids))) { > > mask = BIT(INTEL_SUBPLATFORM_PORTF); > > + } else if (find_devid(devid, subplatform_uy_ids, > > + ARRAY_SIZE(subplatform_uy_ids))) { > > + mask = BIT(INTEL_SUBPLATFORM_UY); > > } else if (find_devid(devid, subplatform_n_ids, > > ARRAY_SIZE(subplatform_n_ids))) { > > mask = BIT(INTEL_SUBPLATFORM_N); > > @@ -243,25 +250,6 @@ void intel_device_info_subplatform_init(struct drm_i915_private *i915) > > mask = BIT(INTEL_SUBPLATFORM_G12); > > } > > - if (IS_TIGERLAKE(i915)) { > > - struct pci_dev *root, *pdev = to_pci_dev(i915->drm.dev); > > - > > - root = list_first_entry(&pdev->bus->devices, typeof(*root), bus_list); > > - > > - drm_WARN_ON(&i915->drm, mask); > > - drm_WARN_ON(&i915->drm, (root->device & TGL_ROOT_DEVICE_MASK) != > > - TGL_ROOT_DEVICE_ID); > > - > > - switch (root->device & TGL_ROOT_DEVICE_SKU_MASK) { > > - case TGL_ROOT_DEVICE_SKU_ULX: > > - mask = BIT(INTEL_SUBPLATFORM_ULX); > > - break; > > - case TGL_ROOT_DEVICE_SKU_ULT: > > - mask = BIT(INTEL_SUBPLATFORM_ULT); > > - break; > > - } > > - } > > - > > GEM_BUG_ON(mask & ~INTEL_SUBPLATFORM_MASK); > > RUNTIME_INFO(i915)->platform_mask[pi] |= mask; > > diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h > > index 2508a47fb3f5e..291215d9da282 100644 > > --- a/drivers/gpu/drm/i915/intel_device_info.h > > +++ b/drivers/gpu/drm/i915/intel_device_info.h > > @@ -106,6 +106,9 @@ enum intel_platform { > > /* ICL */ > > #define INTEL_SUBPLATFORM_PORTF (0) > > +/* TGL */ > > +#define INTEL_SUBPLATFORM_UY (0) > > + > > /* DG2 */ > > #define INTEL_SUBPLATFORM_G10 0 > > #define INTEL_SUBPLATFORM_G11 1 > > diff --git a/drivers/gpu/drm/i915/intel_step.c b/drivers/gpu/drm/i915/intel_step.c > > index ac1a796b28084..4fd69ecd14811 100644 > > --- a/drivers/gpu/drm/i915/intel_step.c > > +++ b/drivers/gpu/drm/i915/intel_step.c > > @@ -165,7 +165,7 @@ void intel_step_init(struct drm_i915_private *i915) > > } else if (IS_ROCKETLAKE(i915)) { > > revids = rkl_revids; > > size = ARRAY_SIZE(rkl_revids); > > - } else if (IS_TGL_U(i915) || IS_TGL_Y(i915)) { > > + } else if (IS_TGL_UY(i915)) { > > revids = tgl_uy_revids; > > size = ARRAY_SIZE(tgl_uy_revids); > > } else if (IS_TIGERLAKE(i915)) {
Best regards, He,Yu -----Original Message----- From: Zhenyu Wang <zhenyuw@linux.intel.com> Sent: 2022年2月23日 11:29 To: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Cc: Souza, Jose <jose.souza@intel.com>; intel-gfx@lists.freedesktop.org; Gao, Fred <fred.gao@intel.com>; He, Yu <yu.he@intel.com> Subject: Re: [Intel-gfx] [PATCH v2] drm/i915/tgl: Simply subplatform detection On 2022.02.22 14:21:33 +0000, Tvrtko Ursulin wrote: > > On 22/02/2022 14:14, Jos?? Roberto de Souza wrote: > > In the past we had a need to differentiate TGL U and TGL Y, there > > was a different voltage swing table for each subplatform and some > > PCI ids of this subplatforms are shared but it turned out that it > > was a specification mistake and the voltage swing table was indeed > > the same but we went ahead with that patch because we needed to > > differentiate TGL U and Y from TGL H and by that time TGL H was > > embargoed so that was the perfect way to land it upstream. > > > > Now the embargo for TGL H is long past and now we even have > > INTEL_TGL_12_GT1_IDS with all TGL H ids, so we can drop this PCI > > root check and only rely in the PCI ids to differentiate TGL U and Y > > from TGL H that actually has code differences. > > > > Besides the simplification this will fix issues in virtualization > > environments where the PCI root is virtualized and don't have the > > same id as actual hardware. > > > > v2: > > - add and set INTEL_SUBPLATFORM_UY > > LGTM, thanks for the tweak! > > Looks mechanical enough so: > > Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> > Add Yu, who has been testing this under GPU passthrough case as well, which now release our effort for root pci device info passthrough issue. Thanks! > > > Cc: Fred Gao <fred.gao@intel.com> > > Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> > > Signed-off-by: Jos?? Roberto de Souza <jose.souza@intel.com> > > --- > > .../drm/i915/display/intel_ddi_buf_trans.c | 2 +- > > drivers/gpu/drm/i915/i915_drv.h | 11 +++----- > > drivers/gpu/drm/i915/i915_reg.h | 6 ----- > > drivers/gpu/drm/i915/intel_device_info.c | 26 +++++-------------- > > drivers/gpu/drm/i915/intel_device_info.h | 3 +++ > > drivers/gpu/drm/i915/intel_step.c | 2 +- > > 6 files changed, 16 insertions(+), 34 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c > > b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c > > index 0c32210bf5031..934a9f9e7dabb 100644 > > --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c > > +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c > > @@ -1321,7 +1321,7 @@ tgl_get_combo_buf_trans_dp(struct intel_encoder *encoder, > > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > > if (crtc_state->port_clock > 270000) { > > - if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv)) { > > + if (IS_TGL_UY(dev_priv)) { > > return intel_get_buf_trans(&tgl_uy_combo_phy_trans_dp_hbr2, > > n_entries); > > } else { > > diff --git a/drivers/gpu/drm/i915/i915_drv.h > > b/drivers/gpu/drm/i915/i915_drv.h index 1c2f4ae4ebf98..51417e9b740f4 > > 100644 > > --- a/drivers/gpu/drm/i915/i915_drv.h > > +++ b/drivers/gpu/drm/i915/i915_drv.h > > @@ -1147,11 +1147,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, > > #define IS_ICL_WITH_PORT_F(dev_priv) \ > > IS_SUBPLATFORM(dev_priv, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF) > > -#define IS_TGL_U(dev_priv) \ > > - IS_SUBPLATFORM(dev_priv, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_ULT) > > - > > -#define IS_TGL_Y(dev_priv) \ > > - IS_SUBPLATFORM(dev_priv, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_ULX) > > +#define IS_TGL_UY(dev_priv) \ > > + IS_SUBPLATFORM(dev_priv, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_UY) > > #define IS_SKL_GRAPHICS_STEP(p, since, until) (IS_SKYLAKE(p) && > > IS_GRAPHICS_STEP(p, since, until)) @@ -1170,11 +1167,11 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, > > IS_DISPLAY_STEP(__i915, since, until)) > > #define IS_TGL_UY_GRAPHICS_STEP(__i915, since, until) \ > > - ((IS_TGL_U(__i915) || IS_TGL_Y(__i915)) && \ > > + (IS_TGL_UY(__i915) && \ > > IS_GRAPHICS_STEP(__i915, since, until)) > > #define IS_TGL_GRAPHICS_STEP(__i915, since, until) \ > > - (IS_TIGERLAKE(__i915) && !(IS_TGL_U(__i915) || IS_TGL_Y(__i915)) && \ > > + (IS_TIGERLAKE(__i915) && !IS_TGL_UY(__i915)) && \ > > IS_GRAPHICS_STEP(__i915, since, until)) > > #define IS_RKL_DISPLAY_STEP(p, since, until) \ diff --git > > a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > > index 2b8a3086ed35a..30aa1d99f2244 100644 > > --- a/drivers/gpu/drm/i915/i915_reg.h > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > @@ -8823,12 +8823,6 @@ enum skl_power_gate { > > #define DSB_ENABLE (1 << 31) > > #define DSB_STATUS (1 << 0) > > -#define TGL_ROOT_DEVICE_ID 0x9A00 > > -#define TGL_ROOT_DEVICE_MASK 0xFF00 > > -#define TGL_ROOT_DEVICE_SKU_MASK 0xF > > -#define TGL_ROOT_DEVICE_SKU_ULX 0x2 > > -#define TGL_ROOT_DEVICE_SKU_ULT 0x4 > > - > > #define CLKREQ_POLICY _MMIO(0x101038) > > #define CLKREQ_POLICY_MEM_UP_OVRD REG_BIT(1) > > diff --git a/drivers/gpu/drm/i915/intel_device_info.c > > b/drivers/gpu/drm/i915/intel_device_info.c > > index ae13bc3c7970e..d03de76147912 100644 > > --- a/drivers/gpu/drm/i915/intel_device_info.c > > +++ b/drivers/gpu/drm/i915/intel_device_info.c > > @@ -170,6 +170,10 @@ static const u16 subplatform_portf_ids[] = { > > INTEL_ICL_PORT_F_IDS(0), > > }; > > +static const u16 subplatform_uy_ids[] = { > > + INTEL_TGL_12_GT2_IDS(0), > > +}; > > + > > static const u16 subplatform_n_ids[] = { > > INTEL_ADLN_IDS(0), > > }; > > @@ -226,6 +230,9 @@ void intel_device_info_subplatform_init(struct drm_i915_private *i915) > > } else if (find_devid(devid, subplatform_portf_ids, > > ARRAY_SIZE(subplatform_portf_ids))) { > > mask = BIT(INTEL_SUBPLATFORM_PORTF); > > + } else if (find_devid(devid, subplatform_uy_ids, > > + ARRAY_SIZE(subplatform_uy_ids))) { > > + mask = BIT(INTEL_SUBPLATFORM_UY); > > } else if (find_devid(devid, subplatform_n_ids, > > ARRAY_SIZE(subplatform_n_ids))) { > > mask = BIT(INTEL_SUBPLATFORM_N); @@ -243,25 +250,6 @@ void > > intel_device_info_subplatform_init(struct drm_i915_private *i915) > > mask = BIT(INTEL_SUBPLATFORM_G12); > > } > > - if (IS_TIGERLAKE(i915)) { > > - struct pci_dev *root, *pdev = to_pci_dev(i915->drm.dev); > > - > > - root = list_first_entry(&pdev->bus->devices, typeof(*root), bus_list); > > - > > - drm_WARN_ON(&i915->drm, mask); > > - drm_WARN_ON(&i915->drm, (root->device & TGL_ROOT_DEVICE_MASK) != > > - TGL_ROOT_DEVICE_ID); > > - > > - switch (root->device & TGL_ROOT_DEVICE_SKU_MASK) { > > - case TGL_ROOT_DEVICE_SKU_ULX: > > - mask = BIT(INTEL_SUBPLATFORM_ULX); > > - break; > > - case TGL_ROOT_DEVICE_SKU_ULT: > > - mask = BIT(INTEL_SUBPLATFORM_ULT); > > - break; > > - } > > - } > > - > > GEM_BUG_ON(mask & ~INTEL_SUBPLATFORM_MASK); > > RUNTIME_INFO(i915)->platform_mask[pi] |= mask; diff --git > > a/drivers/gpu/drm/i915/intel_device_info.h > > b/drivers/gpu/drm/i915/intel_device_info.h > > index 2508a47fb3f5e..291215d9da282 100644 > > --- a/drivers/gpu/drm/i915/intel_device_info.h > > +++ b/drivers/gpu/drm/i915/intel_device_info.h > > @@ -106,6 +106,9 @@ enum intel_platform { > > /* ICL */ > > #define INTEL_SUBPLATFORM_PORTF (0) > > +/* TGL */ > > +#define INTEL_SUBPLATFORM_UY (0) > > + > > /* DG2 */ > > #define INTEL_SUBPLATFORM_G10 0 > > #define INTEL_SUBPLATFORM_G11 1 > > diff --git a/drivers/gpu/drm/i915/intel_step.c > > b/drivers/gpu/drm/i915/intel_step.c > > index ac1a796b28084..4fd69ecd14811 100644 > > --- a/drivers/gpu/drm/i915/intel_step.c > > +++ b/drivers/gpu/drm/i915/intel_step.c > > @@ -165,7 +165,7 @@ void intel_step_init(struct drm_i915_private *i915) > > } else if (IS_ROCKETLAKE(i915)) { > > revids = rkl_revids; > > size = ARRAY_SIZE(rkl_revids); > > - } else if (IS_TGL_U(i915) || IS_TGL_Y(i915)) { > > + } else if (IS_TGL_UY(i915)) { > > revids = tgl_uy_revids; > > size = ARRAY_SIZE(tgl_uy_revids); > > } else if (IS_TIGERLAKE(i915)) { We verified this patch on TGL, and also ran some Linux media/3D cases, no i915 error found in guest dmesg. Tested-by: Yu He <yu.he@intel.com>
On Wed, 2022-02-23 at 11:03 +0000, Patchwork wrote:
Patch Details
Series: drm/i915/tgl: Simply subplatform detection (rev2)
URL: https://patchwork.freedesktop.org/series/100517/
State: failure
Details: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22354/index.html
CI Bug Log - changes from CI_DRM_11268_full -> Patchwork_22354_full
Summary
FAILURE
Serious unknown changes coming with Patchwork_22354_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_22354_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (13 -> 13)
No changes in participating hosts
Possible new issues
Here are the unknown changes that may have been introduced in Patchwork_22354_full:
Piglit changes
Possible regressions
* spec@glsl-4.20@execution@vs_in@vs-input-float_mat4x2-double_dvec3_array2-position:
* pig-skl-6260u: NOTRUN -> FAIL<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22354/pig-skl-6260u/spec@glsl-4.20@execution@vs_in@vs-input-float_mat4x2-double_dvec3_array2-position.html> +415 similar issues
* spec@glsl-4.20@execution@vs_in@vs-input-int_ivec3_array3-double_dvec2_array2-position:
* pig-skl-6260u: NOTRUN -> INCOMPLETE<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22354/pig-skl-6260u/spec@glsl-4.20@execution@vs_in@vs-input-int_ivec3_array3-double_dvec2_array2-position.html> +3 similar issues
Warnings
* spec@glsl-4.20@execution@vs_in@vs-input-double_dmat2x4_array5-position-uint_uvec3:
* pig-skl-6260u: INCOMPLETE<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11268/pig-skl-6260u/spec@glsl-4.20@execution@vs_in@vs-input-double_dmat2x4_array5-position-uint_uvec3.html> -> FAIL<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22354/pig-skl-6260u/spec@glsl-4.20@execution@vs_in@vs-input-double_dmat2x4_array5-position-uint_uvec3.html> +3 similar issues
This patch only affects TGL.
Pushed to drm-intel-gt-next, thanks for the review Tvrtko.
Known issues
Here are the changes found in Patchwork_22354_full that come from known issues:
IGT changes
Issues hit
* igt@feature_discovery@display-3x:
* shard-iclb: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22354/shard-iclb8/igt@feature_discovery@display-3x.html> ([i915#1839])
* igt@gem_exec_capture@pi@vcs0:
* shard-iclb: NOTRUN -> INCOMPLETE<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22354/shard-iclb8/igt@gem_exec_capture@pi@vcs0.html> ([i915#3371])
* igt@gem_exec_fair@basic-none-share@rcs0:
* shard-tglb: PASS<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11268/shard-tglb6/igt@gem_exec_fair@basic-none-share@rcs0.html> -> FAIL<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22354/shard-tglb5/igt@gem_exec_fair@basic-none-share@rcs0.html> ([i915#2842])
* igt@gem_exec_fair@basic-none@vcs1:
* shard-iclb: NOTRUN -> FAIL<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22354/shard-iclb4/igt@gem_exec_fair@basic-none@vcs1.html> ([i915#2842])
* igt@gem_exec_fair@basic-pace-share@rcs0:
* shard-glk: PASS<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11268/shard-glk1/igt@gem_exec_fair@basic-pace-share@rcs0.html> -> FAIL<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22354/shard-glk6/igt@gem_exec_fair@basic-pace-share@rcs0.html> ([i915#2842])
* igt@gem_exec_fair@basic-pace@bcs0:
* shard-iclb: PASS<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11268/shard-iclb7/igt@gem_exec_fair@basic-pace@bcs0.html> -> FAIL<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22354/shard-iclb6/igt@gem_exec_fair@basic-pace@bcs0.html> ([i915#2842])
* igt@gem_exec_params@no-blt:
* shard-tglb: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22354/shard-tglb2/igt@gem_exec_params@no-blt.html> ([fdo#109283])
* shard-iclb: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22354/shard-iclb5/igt@gem_exec_params@no-blt.html> ([fdo#109283])
* igt@gem_lmem_swapping@basic:
* shard-iclb: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22354/shard-iclb5/igt@gem_lmem_swapping@basic.html> ([i915#4613])
* shard-tglb: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22354/shard-tglb2/igt@gem_lmem_swapping@basic.html> ([i915#4613])
* igt@gem_pxp@regular-baseline-src-copy-readible:
* shard-tglb: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22354/shard-tglb2/igt@gem_pxp@regular-baseline-src-copy-readible.html> ([i915#4270])
* igt@gem_pxp@reject-modify-context-protection-off-1:
* shard-iclb: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22354/shard-iclb8/igt@gem_pxp@reject-modify-context-protection-off-1.html> ([i915#4270]) +1 similar issue
* igt@gem_render_copy@linear-to-vebox-yf-tiled:
* shard-iclb: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22354/shard-iclb1/igt@gem_render_copy@linear-to-vebox-yf-tiled.html> ([i915#768]) +1 similar issue
* igt@gem_userptr_blits@unsync-unmap:
* shard-iclb: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22354/shard-iclb5/igt@gem_userptr_blits@unsync-unmap.html> ([i915#3297])
* shard-tglb: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22354/shard-tglb2/igt@gem_userptr_blits@unsync-unmap.html> ([i915#3297])
* igt@gen9_exec_parse@valid-registers:
* shard-iclb: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22354/shard-iclb5/igt@gen9_exec_parse@valid-registers.html> ([i915#2856]) +1 similar issue
* igt@i915_pm_lpsp@screens-disabled:
* shard-tglb: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22354/shard-tglb6/igt@i915_pm_lpsp@screens-disabled.html> ([i915#1902])
* igt@kms_big_fb@linear-32bpp-rotate-0:
* shard-glk: PASS<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11268/shard-glk5/igt@kms_big_fb@linear-32bpp-rotate-0.html> -> DMESG-WARN<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22354/shard-glk6/igt@kms_big_fb@linear-32bpp-rotate-0.html> ([i915#118])
* igt@kms_big_fb@linear-64bpp-rotate-90:
* shard-tglb: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22354/shard-tglb6/igt@kms_big_fb@linear-64bpp-rotate-90.html> ([fdo#111614])
* igt@kms_ccs@pipe-a-bad-pixel-format-y_tiled_ccs:
* shard-tglb: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22354/shard-tglb2/igt@kms_ccs@pipe-a-bad-pixel-format-y_tiled_ccs.html> ([i915#3689]) +1 similar issue
* igt@kms_ccs@pipe-b-bad-aux-stride-y_tiled_gen12_mc_ccs:
* shard-iclb: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22354/shard-iclb8/igt@kms_ccs@pipe-b-bad-aux-stride-y_tiled_gen12_mc_ccs.html> ([fdo#109278] / [i915#3886]) +2 similar issues
* igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_gen12_mc_ccs:
* shard-tglb: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22354/shard-tglb6/igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_gen12_mc_ccs.html> ([i915#3689] / [i915#3886]) +1 similar issue
* igt@kms_color_chamelium@pipe-c-gamma:
* shard-iclb: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22354/shard-iclb5/igt@kms_color_chamelium@pipe-c-gamma.html> ([fdo#109284] / [fdo#111827]) +1 similar issue
* igt@kms_color_chamelium@pipe-d-degamma:
* shard-tglb: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22354/shard-tglb6/igt@kms_color_chamelium@pipe-d-degamma.html> ([fdo#109284] / [fdo#111827]) +2 similar issues
* shard-iclb: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22354/shard-iclb1/igt@kms_color_chamelium@pipe-d-degamma.html> ([fdo#109278] / [fdo#109284] / [fdo#111827])
* igt@kms_content_protection@content_type_change:
* shard-iclb: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22354/shard-iclb8/igt@kms_content_protection@content_type_change.html> ([fdo#109300] / [fdo#111066]) +1 similar issue
* igt@kms_cursor_crc@pipe-a-cursor-64x64-onscreen:
* shard-glk: PASS<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11268/shard-glk5/igt@kms_cursor_crc@pipe-a-cursor-64x64-onscreen.html> -> FAIL<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22354/shard-glk6/igt@kms_cursor_crc@pipe-a-cursor-64x64-onscreen.html> ([i915#3444])
* igt@kms_cursor_crc@pipe-c-cursor-512x170-onscreen:
* shard-tglb: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22354/shard-tglb6/igt@kms_cursor_crc@pipe-c-cursor-512x170-onscreen.html> ([fdo#109279] / [i915#3359])
* igt@kms_cursor_crc@pipe-c-cursor-512x170-rapid-movement:
* shard-iclb: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22354/shard-iclb8/igt@kms_cursor_crc@pipe-c-cursor-512x170-rapid-movement.html> ([fdo#109278]) +8 similar issues
* igt@kms_cursor_legacy@2x-long-nonblocking-modeset-vs-cursor-atomic:
* shard-tglb: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22354/shard-tglb6/igt@kms_cursor_legacy@2x-long-nonblocking-modeset-vs-cursor-atomic.html> ([fdo#109274] / [fdo#111825]) +2 similar issues
* igt@kms_cursor_legacy@cursora-vs-flipb-atomic:
* shard-iclb: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22354/shard-iclb8/igt@kms_cursor_legacy@cursora-vs-flipb-atomic.html> ([fdo#109274] / [fdo#109278])
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
* shard-tglb: PASS<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11268/shard-tglb2/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html> -> FAIL<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22354/shard-tglb5/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html> ([i915#2346] / [i915#533])
* igt@kms_dp_tiled_display@basic-test-pattern-with-chamelium:
* shard-iclb: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22354/shard-iclb8/igt@kms_dp_tiled_display@basic-test-pattern-with-chamelium.html> ([i915#3528])
* igt@kms_flip@2x-absolute-wf_vblank-interruptible:
* shard-iclb: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22354/shard-iclb5/igt@kms_flip@2x-absolute-wf_vblank-interruptible.html> ([fdo#109274])
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ac-hdmi-a1-hdmi-a2:
* shard-glk: PASS<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11268/shard-glk2/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ac-hdmi-a1-hdmi-a2.html> -> FAIL<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22354/shard-glk3/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ac-hdmi-a1-hdmi-a2.html> ([i915#79]) +1 similar issue
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-downscaling:
* shard-iclb: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22354/shard-iclb8/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-downscaling.html> ([i915#2587])
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling:
* shard-glk: PASS<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11268/shard-glk7/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling.html> -> FAIL<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22354/shard-glk8/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling.html> ([i915#4911])
* igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling:
* shard-tglb: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22354/shard-tglb2/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling.html> ([i915#2587])
* igt@kms_force_connector_basic@force-load-detect:
* shard-iclb: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22354/shard-iclb5/igt@kms_force_connector_basic@force-load-detect.html> ([fdo#109285])
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-msflip-blt:
* shard-tglb: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22354/shard-tglb6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-msflip-blt.html> ([fdo#109280] / [fdo#111825]) +2 similar issues
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-shrfb-plflip-blt:
* shard-iclb: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22354/shard-iclb5/igt@kms_frontbuffer_tracking@psr-2p-primscrn-shrfb-plflip-blt.html> ([fdo#109280]) +7 similar issues
* igt@kms_hdr@static-toggle-suspend:
* shard-tglb: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22354/shard-tglb2/igt@kms_hdr@static-toggle-suspend.html> ([i915#1187])
* shard-iclb: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22354/shard-iclb5/igt@kms_hdr@static-toggle-suspend.html> ([i915#1187])
* igt@kms_pipe_b_c_ivb@pipe-b-double-modeset-then-modeset-pipe-c:
* shard-tglb: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22354/shard-tglb6/igt@kms_pipe_b_c_ivb@pipe-b-double-modeset-then-modeset-pipe-c.html> ([fdo#109289])
* shard-iclb: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22354/shard-iclb1/igt@kms_pipe_b_c_ivb@pipe-b-double-modeset-then-modeset-pipe-c.html> ([fdo#109289]) +1 similar issue
* igt@kms_plane_multiple@atomic-pipe-a-tiling-yf:
* shard-tglb: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22354/shard-tglb2/igt@kms_plane_multiple@atomic-pipe-a-tiling-yf.html> ([fdo#111615])
* igt@kms_psr2_su@frontbuffer-xrgb8888:
* shard-iclb: PASS<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11268/shard-iclb2/igt@kms_psr2_su@frontbuffer-xrgb8888.html> -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22354/shard-iclb1/igt@kms_psr2_su@frontbuffer-xrgb8888.html> ([fdo#109642] / [fdo#111068] / [i915#658])
* igt@kms_psr@psr2_primary_render:
* shard-iclb: PASS<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11268/shard-iclb2/igt@kms_psr@psr2_primary_render.html> -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22354/shard-iclb6/igt@kms_psr@psr2_primary_render.html> ([fdo#109441])
* igt@kms_vrr@flip-suspend:
* shard-iclb: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22354/shard-iclb5/igt@kms_vrr@flip-suspend.html> ([fdo#109502])
* igt@nouveau_crc@pipe-b-source-outp-inactive:
* shard-iclb: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22354/shard-iclb1/igt@nouveau_crc@pipe-b-source-outp-inactive.html> ([i915#2530]) +1 similar issue
* shard-tglb: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22354/shard-tglb6/igt@nouveau_crc@pipe-b-source-outp-inactive.html> ([i915#2530])
* igt@prime_nv_pcopy@test3_3:
* shard-iclb: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22354/shard-iclb8/igt@prime_nv_pcopy@test3_3.html> ([fdo#109291]) +1 similar issue
* igt@prime_nv_pcopy@test_semaphore:
* shard-tglb: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22354/shard-tglb2/igt@prime_nv_pcopy@test_semaphore.html> ([fdo#109291])
Possible fixes
* igt@drm_read@short-buffer-nonblock:
* {shard-rkl}: SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11268/shard-rkl-2/igt@drm_read@short-buffer-nonblock.html> ([i915#4098]) -> PASS<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22354/shard-rkl-6/igt@drm_read@short-buffer-nonblock.html> +2 similar issues
* igt@fbdev@info:
* {shard-rkl}: SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11268/shard-rkl-2/igt@fbdev@info.html> ([i915#2582]) -> PASS<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22354/shard-rkl-6/igt@fbdev@info.html>
* igt@gem_ctx_persistence@many-contexts:
* {shard-rkl}: (FAIL<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11268/shard-rkl-4/igt@gem_ctx_persistence@many-contexts.html>, PASS<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11268/shard-rkl-1/igt@gem_ctx_persistence@many-contexts.html>) ([i915#2410]) -> PASS<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22354/shard-rkl-1/igt@gem_ctx_persistence@many-contexts.html>
* igt@gem_eio@unwedge-stress:
* {shard-rkl}: TIMEOUT<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11268/shard-rkl-2/igt@gem_eio@unwedge-stress.html> ([i915#3063]) -> PASS<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22354/shard-rkl-6/igt@gem_eio@unwedge-stress.html>
* igt@gem_exec_fair@basic-flow@rcs0:
* shard-tglb: FAIL<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11268/shard-tglb6/igt@gem_exec_fair@basic-flow@rcs0.html> ([i915#2842]) -> PASS<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22354/shard-tglb5/igt@gem_exec_fair@basic-flow@rcs0.html> +1 similar issue
* igt@gem_lmem_swapping@smem-oom@lmem0:
* {shard-dg1}: DMESG-WARN<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11268/shard-dg1-18/igt@gem_lmem_swapping@smem-oom@lmem0.html> ([i915#4936]) -> PASS<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22354/shard-dg1-15/igt@gem_lmem_swapping@smem-oom@lmem0.html>
* igt@i915_pm_rpm@cursor-dpms:
* {shard-rkl}: (SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11268/shard-rkl-2/igt@i915_pm_rpm@cursor-dpms.html>, SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11268/shard-rkl-4/igt@i915_pm_rpm@cursor-dpms.html>) ([i915#1849]) -> PASS<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22354/shard-rkl-6/igt@i915_pm_rpm@cursor-dpms.html>
* igt@i915_pm_rpm@fences-dpms:
* {shard-rkl}: (PASS<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11268/shard-rkl-6/igt@i915_pm_rpm@fences-dpms.html>, SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11268/shard-rkl-4/igt@i915_pm_rpm@fences-dpms.html>) ([i915#1849]) -> PASS<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22354/shard-rkl-6/igt@i915_pm_rpm@fences-dpms.html>
* igt@i915_pm_rpm@pm-tiling:
* {shard-rkl}: SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11268/shard-rkl-2/igt@i915_pm_rpm@pm-tiling.html> ([fdo#109308]) -> PASS<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22354/shard-rkl-6/igt@i915_pm_rpm@pm-tiling.html> +1 similar issue
* igt@i915_pm_rps@reset:
* {shard-rkl}: FAIL<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11268/shard-rkl-2/igt@i915_pm_rps@reset.html> ([i915#4016]) -> PASS<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22354/shard-rkl-6/igt@i915_pm_rps@reset.html> +1 similar issue
* igt@kms_big_fb@linear-max-hw-stride-32bpp-rotate-0:
* {shard-rkl}: (PASS<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11268/shard-rkl-6/igt@kms_big_fb@linear-max-hw-stride-32bpp-rotate-0.html>, SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11268/shard-rkl-4/igt@kms_big_fb@linear-max-hw-stride-32bpp-rotate-0.html>) ([i915#1845]) -> PASS<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22354/shard-rkl-6/igt@kms_big_fb@linear-max-hw-stride-32bpp-rotate-0.html> +1 similar issue
* igt@kms_big_fb@x-tiled-16bpp-rotate-180:
* {shard-rkl}: (SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11268/shard-rkl-2/igt@kms_big_fb@x-tiled-16bpp-rotate-180.html>, SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11268/shard-rkl-4/igt@kms_big_fb@x-tiled-16bpp-rotate-180.html>) ([i915#1845]) -> PASS<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22354/shard-rkl-6/igt@kms_big_fb@x-tiled-16bpp-rotate-180.html> +2 similar issues
* igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0:
* {shard-rkl}: SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11268/shard-rkl-2/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0.html> ([i915#1845]) -> PASS<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22354/shard-rkl-6/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0.html> +16 similar issues
* igt@kms_big_fb@y-tiled-16bpp-rotate-0:
* {shard-dg1}: DMESG-WARN<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11268/shard-dg1-12/igt@kms_big_fb@y-tiled-16bpp-rotate-0.html> ([i915#4892]) -> PASS<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22354/shard-dg1-15/igt@kms_big_fb@y-tiled-16bpp-rotate-0.html>
* igt@kms_big_fb@yf-tiled-32bpp-rotate-0:
* shard-glk: DMESG-WARN<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11268/shard-glk9/igt@kms_big_fb@yf-tiled-32bpp-rotate-0.html> ([i915#118]) -> PASS<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22354/shard-glk4/igt@kms_big_fb@yf-tiled-32bpp-rotate-0.html>
* igt@kms_ccs@pipe-b-bad-aux-stride-y_tiled_gen12_rc_ccs_cc:
* {shard-rkl}: SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11268/shard-rkl-2/igt@kms_ccs@pipe-b-bad-aux-stride-y_tiled_gen12_rc_ccs_cc.html> ([i915#1845] / [i915#4098]) -> PASS<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22354/shard-rkl-6/igt@kms_ccs@pipe-b-bad-aux-stride-y_tiled_gen12_rc_ccs_cc.html>
* igt@kms_color@pipe-a-ctm-0-75:
* {shard-rkl}: SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11268/shard-rkl-2/igt@kms_color@pipe-a-ctm-0-75.html> ([i915#1149] / [i915#1849] / [i915#4070]) -> PASS<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22354/shard-rkl-6/igt@kms_color@pipe-a-ctm-0-75.html> +2 similar issues
* igt@kms_color@pipe-b-ctm-0-5:
* {shard-rkl}: (SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11268/shard-rkl-4/igt@kms_color@pipe-b-ctm-0-5.html>, SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11268/shard-rkl-2/igt@kms_color@pipe-b-ctm-0-5.html>) ([i915#1149] / [i915#1849] / [i915#4070] / [i915#4098]) -> PASS<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22354/shard-rkl-6/igt@kms_color@pipe-b-ctm-0-5.html>
* igt@kms_cursor_crc@pipe-a-cursor-128x42-offscreen:
* {shard-rkl}: SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11268/shard-rkl-2/igt@kms_cursor_crc@pipe-a-cursor-128x42-offscreen.html> ([fdo#112022] / [i915#4070]) -> PASS<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22354/shard-rkl-6/igt@kms_cursor_crc@pipe-a-cursor-128x42-offscreen.html> +3 similar issues
* igt@kms_cursor_crc@pipe-b-cursor-64x21-random:
* {shard-rkl}: SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11268/shard-rkl-4/igt@kms_cursor_crc@pipe-b-cursor-64x21-random.html> ([fdo#112022]) -> PASS<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22354/shard-rkl-6/igt@kms_cursor_crc@pipe-b-cursor-64x21-random.html> +2 similar issues
* igt@kms_cursor_crc@pipe-c-cursor-64x21-sliding:
* shard-glk: FAIL<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11268/shard-glk8/igt@kms_cursor_crc@pipe-c-cursor-64x21-sliding.html> ([i915#1888] / [i915#3444]) -> PASS<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22354/shard-glk1/igt@kms_cursor_crc@pipe-c-cursor-64x21-sliding.html>
* igt@kms_cursor_edge_walk@pipe-b-128x128-right-edge:
* {shard-rkl}: SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11268/shard-rkl-2/igt@kms_cursor_edge_walk@pipe-b-128x128-right-edge.html> ([i915#1849] / [i915#4070]) -> PASS<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22354/shard-rkl-6/igt@kms_cursor_edge_walk@pipe-b-128x128-right-edge.html> +2 similar issues
* igt@kms_cursor_legacy@basic-flip-before-cursor-legacy:
* {shard-rkl}: SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11268/shard-rkl-2/igt@kms_cursor_legacy@basic-flip-before-cursor-legacy.html> ([fdo#111825] / [i915#4070]) -> PASS<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22354/shard-rkl-6/igt@kms_cursor_legacy@basic-flip-before-cursor-legacy.html>
* igt@kms_cursor_legacy@flip-vs-cursor-atomic:
* {shard-rkl}: SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11268/shard-rkl-4/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html> ([fdo#111825]) -> PASS<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22354/shard-rkl-6/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html>
* igt@kms_cursor_legacy@flip-vs-cursor-toggle:
* shard-iclb: FAIL<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11268/shard-iclb7/igt@kms_cursor_legacy@flip-vs-cursor-toggle.html> ([i915#2346]) -> PASS<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22354/shard-iclb6/igt@kms_cursor_legacy@flip-vs-cursor-toggle.html>
* igt@kms_draw_crc@draw-method-xrgb2101010-mmap-gtt-untiled:
* {shard-rkl}: SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11268/shard-rkl-2/igt@kms_draw_crc@draw-method-xrgb2101010-mmap-gtt-untiled.html> ([fdo#111314]) -> PASS<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22354/shard-rkl-6/igt@kms_draw_crc@draw-method-xrgb2101010-mmap-gtt-untiled.html> +2 similar issues
* igt@kms_draw_crc@draw-method-xrgb2101010-pwrite-untiled:
* {shard-rkl}: (SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11268/shard-rkl-4/igt@kms_draw_crc@draw-method-xrgb2101010-pwrite-untiled.html>, SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11268/shard-rkl-2/igt@kms_draw_crc@draw-method-xrgb2101010-pwrite-untiled.html>) ([fdo#111314] / [i915#4098]) -> PASS<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22354/shard-rkl-6/igt@kms_draw_crc@draw-method-xrgb2101010-pwrite-untiled.html>
* igt@kms_flip@2x-flip-vs-modeset-vs-hang@ab-hdmi-a1-hdmi-a2:
* shard-glk: DMESG-WARN<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11268/shard-glk8/igt@kms_flip@2x-flip-vs-modeset-vs-hang@ab-hdmi-a1-hdmi-a2.html> ([i915#118] / [i915#1888]) -> PASS<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22354/shard-glk1/igt@kms_flip@2x-flip-vs-modeset-vs-hang@ab-hdmi-a1-hdmi-a2.html>
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling:
* shard-iclb: SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11268/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling.html> ([i915#3701]) -> PASS<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22354/shard-iclb1/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling.html>
* igt@kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-cpu:
* {shard-rkl}: SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11268/shard-rkl-2/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-cpu.html> ([i915#1849]) -> PASS<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22354/shard-rkl-6/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-cpu.html> +8 similar issues
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-gtt:
* {shard-rkl}: (SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11268/shard-rkl-2/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-gtt.html>, SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11268/shard-rkl-4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-gtt.html>) ([i915#1849] / [i915#4098]) -> PASS<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22354/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-gtt.html> +5 similar issues
* igt@kms_frontbuffer_tracking@fbcpsr-shrfb-scaledprimary:
* {shard-rkl}: (PASS<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11268/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsr-shrfb-scaledprimary.html>, SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11268/shard-rkl-4/igt@kms_frontbuffer_tracking@fbcpsr-shrfb-scaledprimary.html>) ([i915#4098]) -> PASS<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22354/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsr-shrfb-scaledprimary.html>
* igt@kms_invalid_mode@bad-htotal:
* {shard-rkl}: (SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11268/shard-rkl-2/igt@kms_i>, [SKIP][142]) ([i915#4278]) -> [PASS][143]
diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c index 0c32210bf5031..934a9f9e7dabb 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c @@ -1321,7 +1321,7 @@ tgl_get_combo_buf_trans_dp(struct intel_encoder *encoder, struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); if (crtc_state->port_clock > 270000) { - if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv)) { + if (IS_TGL_UY(dev_priv)) { return intel_get_buf_trans(&tgl_uy_combo_phy_trans_dp_hbr2, n_entries); } else { diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 1c2f4ae4ebf98..51417e9b740f4 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1147,11 +1147,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, #define IS_ICL_WITH_PORT_F(dev_priv) \ IS_SUBPLATFORM(dev_priv, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF) -#define IS_TGL_U(dev_priv) \ - IS_SUBPLATFORM(dev_priv, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_ULT) - -#define IS_TGL_Y(dev_priv) \ - IS_SUBPLATFORM(dev_priv, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_ULX) +#define IS_TGL_UY(dev_priv) \ + IS_SUBPLATFORM(dev_priv, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_UY) #define IS_SKL_GRAPHICS_STEP(p, since, until) (IS_SKYLAKE(p) && IS_GRAPHICS_STEP(p, since, until)) @@ -1170,11 +1167,11 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, IS_DISPLAY_STEP(__i915, since, until)) #define IS_TGL_UY_GRAPHICS_STEP(__i915, since, until) \ - ((IS_TGL_U(__i915) || IS_TGL_Y(__i915)) && \ + (IS_TGL_UY(__i915) && \ IS_GRAPHICS_STEP(__i915, since, until)) #define IS_TGL_GRAPHICS_STEP(__i915, since, until) \ - (IS_TIGERLAKE(__i915) && !(IS_TGL_U(__i915) || IS_TGL_Y(__i915)) && \ + (IS_TIGERLAKE(__i915) && !IS_TGL_UY(__i915)) && \ IS_GRAPHICS_STEP(__i915, since, until)) #define IS_RKL_DISPLAY_STEP(p, since, until) \ diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 2b8a3086ed35a..30aa1d99f2244 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -8823,12 +8823,6 @@ enum skl_power_gate { #define DSB_ENABLE (1 << 31) #define DSB_STATUS (1 << 0) -#define TGL_ROOT_DEVICE_ID 0x9A00 -#define TGL_ROOT_DEVICE_MASK 0xFF00 -#define TGL_ROOT_DEVICE_SKU_MASK 0xF -#define TGL_ROOT_DEVICE_SKU_ULX 0x2 -#define TGL_ROOT_DEVICE_SKU_ULT 0x4 - #define CLKREQ_POLICY _MMIO(0x101038) #define CLKREQ_POLICY_MEM_UP_OVRD REG_BIT(1) diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c index ae13bc3c7970e..d03de76147912 100644 --- a/drivers/gpu/drm/i915/intel_device_info.c +++ b/drivers/gpu/drm/i915/intel_device_info.c @@ -170,6 +170,10 @@ static const u16 subplatform_portf_ids[] = { INTEL_ICL_PORT_F_IDS(0), }; +static const u16 subplatform_uy_ids[] = { + INTEL_TGL_12_GT2_IDS(0), +}; + static const u16 subplatform_n_ids[] = { INTEL_ADLN_IDS(0), }; @@ -226,6 +230,9 @@ void intel_device_info_subplatform_init(struct drm_i915_private *i915) } else if (find_devid(devid, subplatform_portf_ids, ARRAY_SIZE(subplatform_portf_ids))) { mask = BIT(INTEL_SUBPLATFORM_PORTF); + } else if (find_devid(devid, subplatform_uy_ids, + ARRAY_SIZE(subplatform_uy_ids))) { + mask = BIT(INTEL_SUBPLATFORM_UY); } else if (find_devid(devid, subplatform_n_ids, ARRAY_SIZE(subplatform_n_ids))) { mask = BIT(INTEL_SUBPLATFORM_N); @@ -243,25 +250,6 @@ void intel_device_info_subplatform_init(struct drm_i915_private *i915) mask = BIT(INTEL_SUBPLATFORM_G12); } - if (IS_TIGERLAKE(i915)) { - struct pci_dev *root, *pdev = to_pci_dev(i915->drm.dev); - - root = list_first_entry(&pdev->bus->devices, typeof(*root), bus_list); - - drm_WARN_ON(&i915->drm, mask); - drm_WARN_ON(&i915->drm, (root->device & TGL_ROOT_DEVICE_MASK) != - TGL_ROOT_DEVICE_ID); - - switch (root->device & TGL_ROOT_DEVICE_SKU_MASK) { - case TGL_ROOT_DEVICE_SKU_ULX: - mask = BIT(INTEL_SUBPLATFORM_ULX); - break; - case TGL_ROOT_DEVICE_SKU_ULT: - mask = BIT(INTEL_SUBPLATFORM_ULT); - break; - } - } - GEM_BUG_ON(mask & ~INTEL_SUBPLATFORM_MASK); RUNTIME_INFO(i915)->platform_mask[pi] |= mask; diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h index 2508a47fb3f5e..291215d9da282 100644 --- a/drivers/gpu/drm/i915/intel_device_info.h +++ b/drivers/gpu/drm/i915/intel_device_info.h @@ -106,6 +106,9 @@ enum intel_platform { /* ICL */ #define INTEL_SUBPLATFORM_PORTF (0) +/* TGL */ +#define INTEL_SUBPLATFORM_UY (0) + /* DG2 */ #define INTEL_SUBPLATFORM_G10 0 #define INTEL_SUBPLATFORM_G11 1 diff --git a/drivers/gpu/drm/i915/intel_step.c b/drivers/gpu/drm/i915/intel_step.c index ac1a796b28084..4fd69ecd14811 100644 --- a/drivers/gpu/drm/i915/intel_step.c +++ b/drivers/gpu/drm/i915/intel_step.c @@ -165,7 +165,7 @@ void intel_step_init(struct drm_i915_private *i915) } else if (IS_ROCKETLAKE(i915)) { revids = rkl_revids; size = ARRAY_SIZE(rkl_revids); - } else if (IS_TGL_U(i915) || IS_TGL_Y(i915)) { + } else if (IS_TGL_UY(i915)) { revids = tgl_uy_revids; size = ARRAY_SIZE(tgl_uy_revids); } else if (IS_TIGERLAKE(i915)) {
In the past we had a need to differentiate TGL U and TGL Y, there was a different voltage swing table for each subplatform and some PCI ids of this subplatforms are shared but it turned out that it was a specification mistake and the voltage swing table was indeed the same but we went ahead with that patch because we needed to differentiate TGL U and Y from TGL H and by that time TGL H was embargoed so that was the perfect way to land it upstream. Now the embargo for TGL H is long past and now we even have INTEL_TGL_12_GT1_IDS with all TGL H ids, so we can drop this PCI root check and only rely in the PCI ids to differentiate TGL U and Y from TGL H that actually has code differences. Besides the simplification this will fix issues in virtualization environments where the PCI root is virtualized and don't have the same id as actual hardware. v2: - add and set INTEL_SUBPLATFORM_UY Cc: Fred Gao <fred.gao@intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> --- .../drm/i915/display/intel_ddi_buf_trans.c | 2 +- drivers/gpu/drm/i915/i915_drv.h | 11 +++----- drivers/gpu/drm/i915/i915_reg.h | 6 ----- drivers/gpu/drm/i915/intel_device_info.c | 26 +++++-------------- drivers/gpu/drm/i915/intel_device_info.h | 3 +++ drivers/gpu/drm/i915/intel_step.c | 2 +- 6 files changed, 16 insertions(+), 34 deletions(-)