| Message ID | 20220301062123.818687-2-tianfei.zhang@intel.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | Add OFS support for DFL driver | expand |
> -----Original Message----- > From: Zhang, Tianfei <tianfei.zhang@intel.com> > Sent: Tuesday, March 1, 2022 2:21 PM > To: Wu, Hao <hao.wu@intel.com>; trix@redhat.com; mdf@kernel.org; Xu, Yilun > <yilun.xu@intel.com>; linux-fpga@vger.kernel.org; linux-doc@vger.kernel.org > Cc: linux-kernel@vger.kernel.org; corbet@lwn.net; Matthew Gerlach > <matthew.gerlach@linux.intel.com>; Zhang, Tianfei <tianfei.zhang@intel.com> > Subject: [PATCH v3 1/5] fpga: dfl: Allow for ports without specific bar space. > > From: Matthew Gerlach <matthew.gerlach@linux.intel.com> > > In OFS, there is a Port device for each PR slot, like Port > control, Port user clock control and Port errors, those feature > devices are linked with DFL. The DFL of Port device was located > in PCIe Bar 0 MMIO space by default, but it also can put into any There is not default BAR for Port. In OFS implementation it could be 0, but not default value for other implementation. > PCIe Bar space. If the BarID (3bits field) in PORTn_OFFSET register > set to invalid means that DFL of Port device is located in the Bar 0 > by default, in this case, it don't need add the Bar 0 into dfl list > twice. So why not just use existing method (e.g. BAR0 + offset) to locate DFL of port? The title is confusing too, PORTs still have its BAR location/space. Hao > > --- > v2: use FME_HDR_NO_PORT_BAR instead of PCI_STD_NUM_BARS. > > Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com> > Signed-off-by: Tianfei Zhang <tianfei.zhang@intel.com> > --- > drivers/fpga/dfl-pci.c | 6 ++++++ > drivers/fpga/dfl.h | 1 + > 2 files changed, 7 insertions(+) > > diff --git a/drivers/fpga/dfl-pci.c b/drivers/fpga/dfl-pci.c > index 4d68719e608f..33545c999c06 100644 > --- a/drivers/fpga/dfl-pci.c > +++ b/drivers/fpga/dfl-pci.c > @@ -258,6 +258,12 @@ static int find_dfls_by_default(struct pci_dev *pcidev, > */ > bar = FIELD_GET(FME_PORT_OFST_BAR_ID, v); > offset = FIELD_GET(FME_PORT_OFST_DFH_OFST, v); > + if (bar >= FME_HDR_NO_PORT_BAR) { > + dev_dbg(&pcidev->dev, "skipping port without > specific BAR space %d\n", > + bar); > + continue; > + } > + > start = pci_resource_start(pcidev, bar) + offset; > len = pci_resource_len(pcidev, bar) - offset; > > diff --git a/drivers/fpga/dfl.h b/drivers/fpga/dfl.h > index 53572c7aced0..1fd493e82dd8 100644 > --- a/drivers/fpga/dfl.h > +++ b/drivers/fpga/dfl.h > @@ -91,6 +91,7 @@ > #define FME_HDR_PORT_OFST(n) (0x38 + ((n) * 0x8)) > #define FME_HDR_BITSTREAM_ID 0x60 > #define FME_HDR_BITSTREAM_MD 0x68 > +#define FME_HDR_NO_PORT_BAR 7 > > /* FME Fab Capability Register Bitfield */ > #define FME_CAP_FABRIC_VERID GENMASK_ULL(7, 0) /* Fabric > version ID */ > -- > 2.26.2
> -----Original Message----- > From: Wu, Hao <hao.wu@intel.com> > Sent: Tuesday, March 1, 2022 2:44 PM > To: Zhang, Tianfei <tianfei.zhang@intel.com>; trix@redhat.com; > mdf@kernel.org; Xu, Yilun <yilun.xu@intel.com>; linux-fpga@vger.kernel.org; > linux-doc@vger.kernel.org > Cc: linux-kernel@vger.kernel.org; corbet@lwn.net; Matthew Gerlach > <matthew.gerlach@linux.intel.com> > Subject: RE: [PATCH v3 1/5] fpga: dfl: Allow for ports without specific bar space. > > > -----Original Message----- > > From: Zhang, Tianfei <tianfei.zhang@intel.com> > > Sent: Tuesday, March 1, 2022 2:21 PM > > To: Wu, Hao <hao.wu@intel.com>; trix@redhat.com; mdf@kernel.org; Xu, > > Yilun <yilun.xu@intel.com>; linux-fpga@vger.kernel.org; > > linux-doc@vger.kernel.org > > Cc: linux-kernel@vger.kernel.org; corbet@lwn.net; Matthew Gerlach > > <matthew.gerlach@linux.intel.com>; Zhang, Tianfei > > <tianfei.zhang@intel.com> > > Subject: [PATCH v3 1/5] fpga: dfl: Allow for ports without specific bar space. > > > > From: Matthew Gerlach <matthew.gerlach@linux.intel.com> > > > > In OFS, there is a Port device for each PR slot, like Port control, > > Port user clock control and Port errors, those feature devices are > > linked with DFL. The DFL of Port device was located in PCIe Bar 0 MMIO > > space by default, but it also can put into any > > There is not default BAR for Port. In OFS implementation it could be 0, but not > default value for other implementation. > > > PCIe Bar space. If the BarID (3bits field) in PORTn_OFFSET register > > set to invalid means that DFL of Port device is located in the Bar 0 > > by default, in this case, it don't need add the Bar 0 into dfl list > > twice. > > So why not just use existing method (e.g. BAR0 + offset) to locate DFL of port? For N6000 card, this BarID in PORTn_OFFSET register was set to 0b111 in RTL, which is larger than the maximum PCI BAR numbe PCI_STD_NUM_BARS, So for software perspective, this means there is no additional the BAR space of this port device, but the DFH of this port device still located in BAR0. > > The title is confusing too, PORTs still have its BAR location/space. > > Hao > > > > > --- > > v2: use FME_HDR_NO_PORT_BAR instead of PCI_STD_NUM_BARS. > > > > Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com> > > Signed-off-by: Tianfei Zhang <tianfei.zhang@intel.com> > > --- > > drivers/fpga/dfl-pci.c | 6 ++++++ > > drivers/fpga/dfl.h | 1 + > > 2 files changed, 7 insertions(+) > > > > diff --git a/drivers/fpga/dfl-pci.c b/drivers/fpga/dfl-pci.c index > > 4d68719e608f..33545c999c06 100644 > > --- a/drivers/fpga/dfl-pci.c > > +++ b/drivers/fpga/dfl-pci.c > > @@ -258,6 +258,12 @@ static int find_dfls_by_default(struct pci_dev *pcidev, > > */ > > bar = FIELD_GET(FME_PORT_OFST_BAR_ID, v); > > offset = FIELD_GET(FME_PORT_OFST_DFH_OFST, v); > > + if (bar >= FME_HDR_NO_PORT_BAR) { > > + dev_dbg(&pcidev->dev, "skipping port without > > specific BAR space %d\n", > > + bar); > > + continue; > > + } > > + > > start = pci_resource_start(pcidev, bar) + offset; > > len = pci_resource_len(pcidev, bar) - offset; > > > > diff --git a/drivers/fpga/dfl.h b/drivers/fpga/dfl.h index > > 53572c7aced0..1fd493e82dd8 100644 > > --- a/drivers/fpga/dfl.h > > +++ b/drivers/fpga/dfl.h > > @@ -91,6 +91,7 @@ > > #define FME_HDR_PORT_OFST(n) (0x38 + ((n) * 0x8)) > > #define FME_HDR_BITSTREAM_ID 0x60 > > #define FME_HDR_BITSTREAM_MD 0x68 > > +#define FME_HDR_NO_PORT_BAR 7 > > > > /* FME Fab Capability Register Bitfield */ > > #define FME_CAP_FABRIC_VERID GENMASK_ULL(7, 0) /* Fabric > > version ID */ > > -- > > 2.26.2
diff --git a/drivers/fpga/dfl-pci.c b/drivers/fpga/dfl-pci.c index 4d68719e608f..33545c999c06 100644 --- a/drivers/fpga/dfl-pci.c +++ b/drivers/fpga/dfl-pci.c @@ -258,6 +258,12 @@ static int find_dfls_by_default(struct pci_dev *pcidev, */ bar = FIELD_GET(FME_PORT_OFST_BAR_ID, v); offset = FIELD_GET(FME_PORT_OFST_DFH_OFST, v); + if (bar >= FME_HDR_NO_PORT_BAR) { + dev_dbg(&pcidev->dev, "skipping port without specific BAR space %d\n", + bar); + continue; + } + start = pci_resource_start(pcidev, bar) + offset; len = pci_resource_len(pcidev, bar) - offset; diff --git a/drivers/fpga/dfl.h b/drivers/fpga/dfl.h index 53572c7aced0..1fd493e82dd8 100644 --- a/drivers/fpga/dfl.h +++ b/drivers/fpga/dfl.h @@ -91,6 +91,7 @@ #define FME_HDR_PORT_OFST(n) (0x38 + ((n) * 0x8)) #define FME_HDR_BITSTREAM_ID 0x60 #define FME_HDR_BITSTREAM_MD 0x68 +#define FME_HDR_NO_PORT_BAR 7 /* FME Fab Capability Register Bitfield */ #define FME_CAP_FABRIC_VERID GENMASK_ULL(7, 0) /* Fabric version ID */