diff mbox series

[v6,18/43] qtests/cxl: Add initial root port and CXL type3 tests

Message ID 20220211120747.3074-19-Jonathan.Cameron@huawei.com
State Superseded
Headers show
Series CXl 2.0 emulation Support | expand

Commit Message

Jonathan Cameron Feb. 11, 2022, 12:07 p.m. UTC 
At this stage we can boot configurations with host bridges,
root ports and type 3 memory devices, so add appropriate
tests.

Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
 tests/qtest/cxl-test.c | 126 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 126 insertions(+)

Comments

Alex Bennée March 1, 2022, 6:11 p.m. UTC | #1 
Jonathan Cameron <Jonathan.Cameron@huawei.com> writes:

> At this stage we can boot configurations with host bridges,
> root ports and type 3 memory devices, so add appropriate
> tests.
>
> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> ---
>  tests/qtest/cxl-test.c | 126 +++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 126 insertions(+)
>
> diff --git a/tests/qtest/cxl-test.c b/tests/qtest/cxl-test.c
> index 1006c8ae4e..1436de40e2 100644
> --- a/tests/qtest/cxl-test.c
> +++ b/tests/qtest/cxl-test.c
> @@ -8,6 +8,47 @@
>  #include "qemu/osdep.h"
>  #include "libqtest-single.h"
>  
> +#define QEMU_PXB_CMD "-machine q35,cxl=on " \
> +                     "-device pxb-cxl,id=cxl.0,bus=pcie.0,bus_nr=52 "
> +
> +#define QEMU_2PXB_CMD "-machine q35,cxl=on " \
> +                      "-device pxb-cxl,id=cxl.0,bus=pcie.0,bus_nr=52 "  \
> +                      "-device pxb-cxl,id=cxl.1,bus=pcie.0,bus_nr=53 "
> +
> +#define QEMU_RP "-device cxl-rp,id=rp0,bus=cxl.0,chassis=0,slot=0 "
> +
> +/* Dual ports on first pxb */
> +#define QEMU_2RP "-device cxl-rp,id=rp0,bus=cxl.0,chassis=0,slot=0 " \
> +                 "-device cxl-rp,id=rp1,bus=cxl.0,chassis=0,slot=1 "
> +
> +/* Dual ports on each of the pxb instances */
> +#define QEMU_4RP "-device cxl-rp,id=rp0,bus=cxl.0,chassis=0,slot=0 " \
> +                 "-device cxl-rp,id=rp1,bus=cxl.0,chassis=0,slot=1 " \
> +                 "-device cxl-rp,id=rp2,bus=cxl.1,chassis=0,slot=2 " \
> +                 "-device cxl-rp,id=rp3,bus=cxl.1,chassis=0,slot=3 "
> +
> +#define QEMU_T3D "-object memory-backend-file,id=cxl-mem0,mem-path=%s,size=256M " \
> +                 "-device cxl-type3,bus=rp0,memdev=cxl-mem0,id=cxl-pmem0,size=256M "
> +
> +#define QEMU_2T3D "-object memory-backend-file,id=cxl-mem0,mem-path=%s,size=256M "    \
> +                  "-device cxl-type3,bus=rp0,memdev=cxl-mem0,id=cxl-pmem0,size=256M " \
> +                  "-object memory-backend-file,id=cxl-mem1,mem-path=%s,size=256M "    \
> +                  "-device cxl-type3,bus=rp1,memdev=cxl-mem1,id=cxl-pmem1,size=256M "
> +
> +#define QEMU_4T3D "-object memory-backend-file,id=cxl-mem0,mem-path=%s,size=256M "    \
> +                  "-device cxl-type3,bus=rp0,memdev=cxl-mem0,id=cxl-pmem0,size=256M " \
> +                  "-object memory-backend-file,id=cxl-mem1,mem-path=%s,size=256M "    \
> +                  "-device cxl-type3,bus=rp1,memdev=cxl-mem1,id=cxl-pmem1,size=256M " \
> +                  "-object memory-backend-file,id=cxl-mem2,mem-path=%s,size=256M "    \
> +                  "-device cxl-type3,bus=rp2,memdev=cxl-mem2,id=cxl-pmem2,size=256M " \
> +                  "-object memory-backend-file,id=cxl-mem3,mem-path=%s,size=256M "    \
> +                  "-device cxl-type3,bus=rp3,memdev=cxl-mem3,id=cxl-pmem3,size=256M "
> +
> +static void cxl_basic_hb(void)
> +{
> +    qtest_start("-machine q35,cxl=on");
> +    qtest_end();
> +}
>  
>  static void cxl_basic_pxb(void)
>  {
> @@ -15,9 +56,94 @@ static void cxl_basic_pxb(void)
>      qtest_end();
>  }
>  
> +static void cxl_pxb_with_window(void)
> +{
> +    qtest_start(QEMU_PXB_CMD);
> +    qtest_end();
> +}
> +
> +static void cxl_2pxb_with_window(void)
> +{
> +    qtest_start(QEMU_2PXB_CMD);
> +    qtest_end();
> +}
> +
> +static void cxl_root_port(void)
> +{
> +    qtest_start(QEMU_PXB_CMD QEMU_RP);
> +    qtest_end();
> +}
> +
> +static void cxl_2root_port(void)
> +{
> +    qtest_start(QEMU_PXB_CMD QEMU_2RP);
> +    qtest_end();
> +}
> +
> +static void cxl_t3d(void)
> +{
> +    GString *cmdline;
> +    char template[] = "/tmp/cxl-test-XXXXXX";
> +    const char *tmpfs;
> +
> +    tmpfs = mkdtemp(template);
> +
> +    cmdline = g_string_new(NULL);
> +    g_string_printf(cmdline, QEMU_PXB_CMD QEMU_RP QEMU_T3D, tmpfs);
> +
> +    qtest_start(cmdline->str);
> +    qtest_end();
> +
> +    g_string_free(cmdline, TRUE);

For future reference you could do:

  g_autoptr(GString) cmdline = g_string_new(NULL);

and drop the free ;-)

> +}
> +
> +static void cxl_1pxb_2rp_2t3d(void)
> +{
> +    GString *cmdline;
> +    char template[] = "/tmp/cxl-test-XXXXXX";
> +    const char *tmpfs;
> +
> +    tmpfs = mkdtemp(template);
> +
> +    cmdline = g_string_new(NULL);
> +    g_string_printf(cmdline, QEMU_PXB_CMD QEMU_2RP QEMU_2T3D, tmpfs, tmpfs);
> +
> +    qtest_start(cmdline->str);
> +    qtest_end();
> +
> +    g_string_free(cmdline, TRUE);
> +}
> +
> +static void cxl_2pxb_4rp_4t3d(void)
> +{
> +    GString *cmdline;
> +    char template[] = "/tmp/cxl-test-XXXXXX";
> +    const char *tmpfs;
> +
> +    tmpfs = mkdtemp(template);
> +
> +    cmdline = g_string_new(NULL);
> +    g_string_printf(cmdline, QEMU_2PXB_CMD QEMU_4RP QEMU_4T3D,
> +                    tmpfs, tmpfs, tmpfs, tmpfs);
> +
> +    qtest_start(cmdline->str);
> +    qtest_end();
> +
> +    g_string_free(cmdline, TRUE);
> +}
> +
>  int main(int argc, char **argv)
>  {
>      g_test_init(&argc, &argv, NULL);
> +
> +    qtest_add_func("/pci/cxl/basic_hostbridge", cxl_basic_hb);
>      qtest_add_func("/pci/cxl/basic_pxb", cxl_basic_pxb);
> +    qtest_add_func("/pci/cxl/pxb_with_window", cxl_pxb_with_window);
> +    qtest_add_func("/pci/cxl/pxb_x2_with_window", cxl_2pxb_with_window);
> +    qtest_add_func("/pci/cxl/rp", cxl_root_port);
> +    qtest_add_func("/pci/cxl/rp_x2", cxl_2root_port);
> +    qtest_add_func("/pci/cxl/type3_device", cxl_t3d);
> +    qtest_add_func("/pci/cxl/rp_x2_type3_x2", cxl_1pxb_2rp_2t3d);
> +    qtest_add_func("/pci/cxl/pxb_x2_root_port_x4_type3_x4", cxl_2pxb_4rp_4t3d);
>      return g_test_run();
>  }

Otherwise:

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Jonathan Cameron March 3, 2022, 5:53 p.m. UTC | #2 
On Tue, 01 Mar 2022 18:11:25 +0000
Alex Bennée <alex.bennee@linaro.org> wrote:

> Jonathan Cameron <Jonathan.Cameron@huawei.com> writes:
> 
> > At this stage we can boot configurations with host bridges,
> > root ports and type 3 memory devices, so add appropriate
> > tests.
> >
> > Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> > ---
> >  tests/qtest/cxl-test.c | 126 +++++++++++++++++++++++++++++++++++++++++
> >  1 file changed, 126 insertions(+)
> >
> > diff --git a/tests/qtest/cxl-test.c b/tests/qtest/cxl-test.c
> > index 1006c8ae4e..1436de40e2 100644
> > --- a/tests/qtest/cxl-test.c
> > +++ b/tests/qtest/cxl-test.c
> > @@ -8,6 +8,47 @@
> >  #include "qemu/osdep.h"
> >  #include "libqtest-single.h"
> >  
> > +#define QEMU_PXB_CMD "-machine q35,cxl=on " \
> > +                     "-device pxb-cxl,id=cxl.0,bus=pcie.0,bus_nr=52 "
> > +
> > +#define QEMU_2PXB_CMD "-machine q35,cxl=on " \
> > +                      "-device pxb-cxl,id=cxl.0,bus=pcie.0,bus_nr=52 "  \
> > +                      "-device pxb-cxl,id=cxl.1,bus=pcie.0,bus_nr=53 "
> > +
> > +#define QEMU_RP "-device cxl-rp,id=rp0,bus=cxl.0,chassis=0,slot=0 "
> > +
> > +/* Dual ports on first pxb */
> > +#define QEMU_2RP "-device cxl-rp,id=rp0,bus=cxl.0,chassis=0,slot=0 " \
> > +                 "-device cxl-rp,id=rp1,bus=cxl.0,chassis=0,slot=1 "
> > +
> > +/* Dual ports on each of the pxb instances */
> > +#define QEMU_4RP "-device cxl-rp,id=rp0,bus=cxl.0,chassis=0,slot=0 " \
> > +                 "-device cxl-rp,id=rp1,bus=cxl.0,chassis=0,slot=1 " \
> > +                 "-device cxl-rp,id=rp2,bus=cxl.1,chassis=0,slot=2 " \
> > +                 "-device cxl-rp,id=rp3,bus=cxl.1,chassis=0,slot=3 "
> > +
> > +#define QEMU_T3D "-object memory-backend-file,id=cxl-mem0,mem-path=%s,size=256M " \
> > +                 "-device cxl-type3,bus=rp0,memdev=cxl-mem0,id=cxl-pmem0,size=256M "
> > +
> > +#define QEMU_2T3D "-object memory-backend-file,id=cxl-mem0,mem-path=%s,size=256M "    \
> > +                  "-device cxl-type3,bus=rp0,memdev=cxl-mem0,id=cxl-pmem0,size=256M " \
> > +                  "-object memory-backend-file,id=cxl-mem1,mem-path=%s,size=256M "    \
> > +                  "-device cxl-type3,bus=rp1,memdev=cxl-mem1,id=cxl-pmem1,size=256M "
> > +
> > +#define QEMU_4T3D "-object memory-backend-file,id=cxl-mem0,mem-path=%s,size=256M "    \
> > +                  "-device cxl-type3,bus=rp0,memdev=cxl-mem0,id=cxl-pmem0,size=256M " \
> > +                  "-object memory-backend-file,id=cxl-mem1,mem-path=%s,size=256M "    \
> > +                  "-device cxl-type3,bus=rp1,memdev=cxl-mem1,id=cxl-pmem1,size=256M " \
> > +                  "-object memory-backend-file,id=cxl-mem2,mem-path=%s,size=256M "    \
> > +                  "-device cxl-type3,bus=rp2,memdev=cxl-mem2,id=cxl-pmem2,size=256M " \
> > +                  "-object memory-backend-file,id=cxl-mem3,mem-path=%s,size=256M "    \
> > +                  "-device cxl-type3,bus=rp3,memdev=cxl-mem3,id=cxl-pmem3,size=256M "
> > +
> > +static void cxl_basic_hb(void)
> > +{
> > +    qtest_start("-machine q35,cxl=on");
> > +    qtest_end();
> > +}
> >  
> >  static void cxl_basic_pxb(void)
> >  {
> > @@ -15,9 +56,94 @@ static void cxl_basic_pxb(void)
> >      qtest_end();
> >  }
> >  
> > +static void cxl_pxb_with_window(void)
> > +{
> > +    qtest_start(QEMU_PXB_CMD);
> > +    qtest_end();
> > +}
> > +
> > +static void cxl_2pxb_with_window(void)
> > +{
> > +    qtest_start(QEMU_2PXB_CMD);
> > +    qtest_end();
> > +}
> > +
> > +static void cxl_root_port(void)
> > +{
> > +    qtest_start(QEMU_PXB_CMD QEMU_RP);
> > +    qtest_end();
> > +}
> > +
> > +static void cxl_2root_port(void)
> > +{
> > +    qtest_start(QEMU_PXB_CMD QEMU_2RP);
> > +    qtest_end();
> > +}
> > +
> > +static void cxl_t3d(void)
> > +{
> > +    GString *cmdline;
> > +    char template[] = "/tmp/cxl-test-XXXXXX";
> > +    const char *tmpfs;
> > +
> > +    tmpfs = mkdtemp(template);
> > +
> > +    cmdline = g_string_new(NULL);
> > +    g_string_printf(cmdline, QEMU_PXB_CMD QEMU_RP QEMU_T3D, tmpfs);
> > +
> > +    qtest_start(cmdline->str);
> > +    qtest_end();
> > +
> > +    g_string_free(cmdline, TRUE);  
> 
> For future reference you could do:
> 
>   g_autoptr(GString) cmdline = g_string_new(NULL);
> 
> and drop the free ;-)

nice. Done here and in later qtest patches.

Thanks,

Jonathan
diff mbox series

Patch

diff --git a/tests/qtest/cxl-test.c b/tests/qtest/cxl-test.c
index 1006c8ae4e..1436de40e2 100644
--- a/tests/qtest/cxl-test.c
+++ b/tests/qtest/cxl-test.c
@@ -8,6 +8,47 @@ 
 #include "qemu/osdep.h"
 #include "libqtest-single.h"
 
+#define QEMU_PXB_CMD "-machine q35,cxl=on " \
+                     "-device pxb-cxl,id=cxl.0,bus=pcie.0,bus_nr=52 "
+
+#define QEMU_2PXB_CMD "-machine q35,cxl=on " \
+                      "-device pxb-cxl,id=cxl.0,bus=pcie.0,bus_nr=52 "  \
+                      "-device pxb-cxl,id=cxl.1,bus=pcie.0,bus_nr=53 "
+
+#define QEMU_RP "-device cxl-rp,id=rp0,bus=cxl.0,chassis=0,slot=0 "
+
+/* Dual ports on first pxb */
+#define QEMU_2RP "-device cxl-rp,id=rp0,bus=cxl.0,chassis=0,slot=0 " \
+                 "-device cxl-rp,id=rp1,bus=cxl.0,chassis=0,slot=1 "
+
+/* Dual ports on each of the pxb instances */
+#define QEMU_4RP "-device cxl-rp,id=rp0,bus=cxl.0,chassis=0,slot=0 " \
+                 "-device cxl-rp,id=rp1,bus=cxl.0,chassis=0,slot=1 " \
+                 "-device cxl-rp,id=rp2,bus=cxl.1,chassis=0,slot=2 " \
+                 "-device cxl-rp,id=rp3,bus=cxl.1,chassis=0,slot=3 "
+
+#define QEMU_T3D "-object memory-backend-file,id=cxl-mem0,mem-path=%s,size=256M " \
+                 "-device cxl-type3,bus=rp0,memdev=cxl-mem0,id=cxl-pmem0,size=256M "
+
+#define QEMU_2T3D "-object memory-backend-file,id=cxl-mem0,mem-path=%s,size=256M "    \
+                  "-device cxl-type3,bus=rp0,memdev=cxl-mem0,id=cxl-pmem0,size=256M " \
+                  "-object memory-backend-file,id=cxl-mem1,mem-path=%s,size=256M "    \
+                  "-device cxl-type3,bus=rp1,memdev=cxl-mem1,id=cxl-pmem1,size=256M "
+
+#define QEMU_4T3D "-object memory-backend-file,id=cxl-mem0,mem-path=%s,size=256M "    \
+                  "-device cxl-type3,bus=rp0,memdev=cxl-mem0,id=cxl-pmem0,size=256M " \
+                  "-object memory-backend-file,id=cxl-mem1,mem-path=%s,size=256M "    \
+                  "-device cxl-type3,bus=rp1,memdev=cxl-mem1,id=cxl-pmem1,size=256M " \
+                  "-object memory-backend-file,id=cxl-mem2,mem-path=%s,size=256M "    \
+                  "-device cxl-type3,bus=rp2,memdev=cxl-mem2,id=cxl-pmem2,size=256M " \
+                  "-object memory-backend-file,id=cxl-mem3,mem-path=%s,size=256M "    \
+                  "-device cxl-type3,bus=rp3,memdev=cxl-mem3,id=cxl-pmem3,size=256M "
+
+static void cxl_basic_hb(void)
+{
+    qtest_start("-machine q35,cxl=on");
+    qtest_end();
+}
 
 static void cxl_basic_pxb(void)
 {
@@ -15,9 +56,94 @@  static void cxl_basic_pxb(void)
     qtest_end();
 }
 
+static void cxl_pxb_with_window(void)
+{
+    qtest_start(QEMU_PXB_CMD);
+    qtest_end();
+}
+
+static void cxl_2pxb_with_window(void)
+{
+    qtest_start(QEMU_2PXB_CMD);
+    qtest_end();
+}
+
+static void cxl_root_port(void)
+{
+    qtest_start(QEMU_PXB_CMD QEMU_RP);
+    qtest_end();
+}
+
+static void cxl_2root_port(void)
+{
+    qtest_start(QEMU_PXB_CMD QEMU_2RP);
+    qtest_end();
+}
+
+static void cxl_t3d(void)
+{
+    GString *cmdline;
+    char template[] = "/tmp/cxl-test-XXXXXX";
+    const char *tmpfs;
+
+    tmpfs = mkdtemp(template);
+
+    cmdline = g_string_new(NULL);
+    g_string_printf(cmdline, QEMU_PXB_CMD QEMU_RP QEMU_T3D, tmpfs);
+
+    qtest_start(cmdline->str);
+    qtest_end();
+
+    g_string_free(cmdline, TRUE);
+}
+
+static void cxl_1pxb_2rp_2t3d(void)
+{
+    GString *cmdline;
+    char template[] = "/tmp/cxl-test-XXXXXX";
+    const char *tmpfs;
+
+    tmpfs = mkdtemp(template);
+
+    cmdline = g_string_new(NULL);
+    g_string_printf(cmdline, QEMU_PXB_CMD QEMU_2RP QEMU_2T3D, tmpfs, tmpfs);
+
+    qtest_start(cmdline->str);
+    qtest_end();
+
+    g_string_free(cmdline, TRUE);
+}
+
+static void cxl_2pxb_4rp_4t3d(void)
+{
+    GString *cmdline;
+    char template[] = "/tmp/cxl-test-XXXXXX";
+    const char *tmpfs;
+
+    tmpfs = mkdtemp(template);
+
+    cmdline = g_string_new(NULL);
+    g_string_printf(cmdline, QEMU_2PXB_CMD QEMU_4RP QEMU_4T3D,
+                    tmpfs, tmpfs, tmpfs, tmpfs);
+
+    qtest_start(cmdline->str);
+    qtest_end();
+
+    g_string_free(cmdline, TRUE);
+}
+
 int main(int argc, char **argv)
 {
     g_test_init(&argc, &argv, NULL);
+
+    qtest_add_func("/pci/cxl/basic_hostbridge", cxl_basic_hb);
     qtest_add_func("/pci/cxl/basic_pxb", cxl_basic_pxb);
+    qtest_add_func("/pci/cxl/pxb_with_window", cxl_pxb_with_window);
+    qtest_add_func("/pci/cxl/pxb_x2_with_window", cxl_2pxb_with_window);
+    qtest_add_func("/pci/cxl/rp", cxl_root_port);
+    qtest_add_func("/pci/cxl/rp_x2", cxl_2root_port);
+    qtest_add_func("/pci/cxl/type3_device", cxl_t3d);
+    qtest_add_func("/pci/cxl/rp_x2_type3_x2", cxl_1pxb_2rp_2t3d);
+    qtest_add_func("/pci/cxl/pxb_x2_root_port_x4_type3_x4", cxl_2pxb_4rp_4t3d);
     return g_test_run();
 }