| Message ID | 1646300401-9063-2-git-send-email-quic_vpolimer@quicinc.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Update mdp clk to max supported value to support higher refresh rates | expand |
Quoting Vinod Polimera (2022-03-03 01:39:58) > Kernel clock driver assumes that initial rate is the > max rate for that clock and was not allowing it to scale > beyond the assigned clock value. > > Drop the assigned clock rate property and vote on the mdp clock as per > calculated value during the usecase. > > Changes in v2: > - Remove assigned-clock-rate property and set mdp clk during resume sequence. > - Add fixes tag. > > Changes in v3: > - Remove extra line after fixes tag.(Stephen Boyd) > This changelog goes below triple dash when they aren't intended for drm. > Fixes: 62fbdce91("arm64: dts: qcom: sc7280: add display dt nodes") > Signed-off-by: Vinod Polimera <quic_vpolimer@quicinc.com> > --- Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Hi, On Thu, Mar 3, 2022 at 1:40 AM Vinod Polimera <quic_vpolimer@quicinc.com> wrote: > > Kernel clock driver assumes that initial rate is the > max rate for that clock and was not allowing it to scale > beyond the assigned clock value. > > Drop the assigned clock rate property and vote on the mdp clock as per > calculated value during the usecase. I see the "Drop the assigned clock rate property" part, but where is the "and vote on the mdp clock" part? Did it already land or something? I definitely see that commit 5752c921d267 ("drm/msm/dpu: simplify clocks handling") changed a bunch of this but it looks like dpu_core_perf_init() still sets "max_core_clk_rate" to whatever the clock was at bootup. I assume you need to modify that function to call into the OPP layer to find the max frequency? > Changes in v2: > - Remove assigned-clock-rate property and set mdp clk during resume sequence. > - Add fixes tag. > > Changes in v3: > - Remove extra line after fixes tag.(Stephen Boyd) > > Fixes: 62fbdce91("arm64: dts: qcom: sc7280: add display dt nodes") Having a "Fixes" is good, but presumably you need a code change along with this, right? Otherwise if someone picks this back to stable then they'll end up breaking, right? We need to tag / note that _somehow_.
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index baf1653..408cf6c 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -2856,9 +2856,6 @@ "ahb", "core"; - assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; - assigned-clock-rates = <300000000>; - interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; #interrupt-cells = <1>; @@ -2892,11 +2889,9 @@ "lut", "core", "vsync"; - assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, - <&dispcc DISP_CC_MDSS_VSYNC_CLK>, + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>, <&dispcc DISP_CC_MDSS_AHB_CLK>; - assigned-clock-rates = <300000000>, - <19200000>, + assigned-clock-rates = <19200000>, <19200000>; operating-points-v2 = <&mdp_opp_table>; power-domains = <&rpmhpd SC7280_CX>;
Kernel clock driver assumes that initial rate is the max rate for that clock and was not allowing it to scale beyond the assigned clock value. Drop the assigned clock rate property and vote on the mdp clock as per calculated value during the usecase. Changes in v2: - Remove assigned-clock-rate property and set mdp clk during resume sequence. - Add fixes tag. Changes in v3: - Remove extra line after fixes tag.(Stephen Boyd) Fixes: 62fbdce91("arm64: dts: qcom: sc7280: add display dt nodes") Signed-off-by: Vinod Polimera <quic_vpolimer@quicinc.com> --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-)