| Message ID | 20220221141127.3765-1-tien.sung.ang@intel.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | fpga: altera-cvp: Increase the credit timeout | expand |
On Mon, Feb 21, 2022 at 10:11:27PM +0800, tien.sung.ang@intel.com wrote: > From: Ang Tien Sung <tien.sung.ang@intel.com> > > Increase the timeout for SDM (Secure device manager) data credits from > 20ms to 40ms. Internal stress tests running at 500 loops failed with the > current timeout of 20ms. At the start of a FPGA configuration, the CVP > host driver reads the transmit credits from SDM. It then sends bitstream > FPGA data to SDM based on the total credits. Each credit allows the > CVP host driver to send 4kBytes of data. There are situations whereby, > the SDM did not respond in time during testing. > > Signed-off-by: Ang Tien Sung <tien.sung.ang@intel.com> > --- > drivers/fpga/altera-cvp.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/fpga/altera-cvp.c b/drivers/fpga/altera-cvp.c > index 4ffb9da537d8..5295ff90482b 100644 > --- a/drivers/fpga/altera-cvp.c > +++ b/drivers/fpga/altera-cvp.c > @@ -52,7 +52,7 @@ > /* V2 Defines */ > #define VSE_CVP_TX_CREDITS 0x49 /* 8bit */ > > -#define V2_CREDIT_TIMEOUT_US 20000 > +#define V2_CREDIT_TIMEOUT_US 40000 > #define V2_CHECK_CREDIT_US 10 > #define V2_POLL_TIMEOUT_US 1000000 > #define V2_USER_TIMEOUT_US 500000 Acked-by: Xu Yilun <yilun.xu@intel.com> > -- > 2.25.1
> Subject: Re: [PATCH] fpga: altera-cvp: Increase the credit timeout > > On Mon, Feb 21, 2022 at 10:11:27PM +0800, tien.sung.ang@intel.com wrote: > > From: Ang Tien Sung <tien.sung.ang@intel.com> > > > > Increase the timeout for SDM (Secure device manager) data credits from > > 20ms to 40ms. Internal stress tests running at 500 loops failed with the > > current timeout of 20ms. At the start of a FPGA configuration, the CVP > > host driver reads the transmit credits from SDM. It then sends bitstream > > FPGA data to SDM based on the total credits. Each credit allows the > > CVP host driver to send 4kBytes of data. There are situations whereby, > > the SDM did not respond in time during testing. Why this timeout is changed to 40ms not 50ms or 60ms? What's the time we expected from SDM? I hope we don't need to change this again. Thanks Hao > > > > Signed-off-by: Ang Tien Sung <tien.sung.ang@intel.com> > > --- > > drivers/fpga/altera-cvp.c | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/drivers/fpga/altera-cvp.c b/drivers/fpga/altera-cvp.c > > index 4ffb9da537d8..5295ff90482b 100644 > > --- a/drivers/fpga/altera-cvp.c > > +++ b/drivers/fpga/altera-cvp.c > > @@ -52,7 +52,7 @@ > > /* V2 Defines */ > > #define VSE_CVP_TX_CREDITS 0x49 /* 8bit */ > > > > -#define V2_CREDIT_TIMEOUT_US 20000 > > +#define V2_CREDIT_TIMEOUT_US 40000 > > #define V2_CHECK_CREDIT_US 10 > > #define V2_POLL_TIMEOUT_US 1000000 > > #define V2_USER_TIMEOUT_US 500000 > > Acked-by: Xu Yilun <yilun.xu@intel.com> > > > -- > > 2.25.1
Hi Hao, We have tested the 40ms change with 500 loops and deem this satisfying based on the recommendations by the Intel FPGA SDM HW team. SDM was expected to respond within a maximum time of 20ms +-error margin. However, there were cases this weren't the case during tests. After many rounds of tests, they conclude that 40ms is doable. And, this is double the previous time-out of 20ms. There is a bigger margin added this time. Overall, we don't intend to increase the time-out any further. Thanks Tien Sung -----Original Message----- From: Wu, Hao <hao.wu@intel.com> Sent: Monday, 28 February, 2022 5:54 PM To: Xu, Yilun <yilun.xu@intel.com>; Ang, Tien Sung <tien.sung.ang@intel.com> Cc: Moritz Fischer <mdf@kernel.org>; Tom Rix <trix@redhat.com>; linux-fpga@vger.kernel.org Subject: RE: [PATCH] fpga: altera-cvp: Increase the credit timeout > Subject: Re: [PATCH] fpga: altera-cvp: Increase the credit timeout > > On Mon, Feb 21, 2022 at 10:11:27PM +0800, tien.sung.ang@intel.com wrote: > > From: Ang Tien Sung <tien.sung.ang@intel.com> > > > > Increase the timeout for SDM (Secure device manager) data credits > > from 20ms to 40ms. Internal stress tests running at 500 loops failed > > with the current timeout of 20ms. At the start of a FPGA > > configuration, the CVP host driver reads the transmit credits from > > SDM. It then sends bitstream FPGA data to SDM based on the total > > credits. Each credit allows the CVP host driver to send 4kBytes of > > data. There are situations whereby, the SDM did not respond in time during testing. Why this timeout is changed to 40ms not 50ms or 60ms? What's the time we expected from SDM? I hope we don't need to change this again. Thanks Hao > > > > Signed-off-by: Ang Tien Sung <tien.sung.ang@intel.com> > > --- > > drivers/fpga/altera-cvp.c | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/drivers/fpga/altera-cvp.c b/drivers/fpga/altera-cvp.c > > index 4ffb9da537d8..5295ff90482b 100644 > > --- a/drivers/fpga/altera-cvp.c > > +++ b/drivers/fpga/altera-cvp.c > > @@ -52,7 +52,7 @@ > > /* V2 Defines */ > > #define VSE_CVP_TX_CREDITS 0x49 /* 8bit */ > > > > -#define V2_CREDIT_TIMEOUT_US 20000 > > +#define V2_CREDIT_TIMEOUT_US 40000 > > #define V2_CHECK_CREDIT_US 10 > > #define V2_POLL_TIMEOUT_US 1000000 > > #define V2_USER_TIMEOUT_US 500000 > > Acked-by: Xu Yilun <yilun.xu@intel.com> > > > -- > > 2.25.1
> -----Original Message----- > From: Ang, Tien Sung <tien.sung.ang@intel.com> > Sent: Friday, March 4, 2022 4:45 PM > To: Wu, Hao <hao.wu@intel.com>; Xu, Yilun <yilun.xu@intel.com> > Cc: Moritz Fischer <mdf@kernel.org>; Tom Rix <trix@redhat.com>; linux- > fpga@vger.kernel.org > Subject: RE: [PATCH] fpga: altera-cvp: Increase the credit timeout > > Hi Hao, > > We have tested the 40ms change with 500 loops and deem this satisfying > based on the recommendations by the Intel FPGA SDM HW team. > SDM was expected to respond within a maximum time of 20ms +-error margin. > However, there were cases this weren't the case during tests. > After many rounds of tests, they conclude that 40ms is doable. > And, this is double the previous time-out of 20ms. > There is a bigger margin added this time. > Overall, we don't intend to increase the time-out any further. I see. Thanks. Acked-by: Wu Hao <hao.wu@intel.com> Hao > Thanks > Tien Sung > > -----Original Message----- > From: Wu, Hao <hao.wu@intel.com> > Sent: Monday, 28 February, 2022 5:54 PM > To: Xu, Yilun <yilun.xu@intel.com>; Ang, Tien Sung <tien.sung.ang@intel.com> > Cc: Moritz Fischer <mdf@kernel.org>; Tom Rix <trix@redhat.com>; linux- > fpga@vger.kernel.org > Subject: RE: [PATCH] fpga: altera-cvp: Increase the credit timeout > > > Subject: Re: [PATCH] fpga: altera-cvp: Increase the credit timeout > > > > On Mon, Feb 21, 2022 at 10:11:27PM +0800, tien.sung.ang@intel.com wrote: > > > From: Ang Tien Sung <tien.sung.ang@intel.com> > > > > > > Increase the timeout for SDM (Secure device manager) data credits > > > from 20ms to 40ms. Internal stress tests running at 500 loops failed > > > with the current timeout of 20ms. At the start of a FPGA > > > configuration, the CVP host driver reads the transmit credits from > > > SDM. It then sends bitstream FPGA data to SDM based on the total > > > credits. Each credit allows the CVP host driver to send 4kBytes of > > > data. There are situations whereby, the SDM did not respond in time during > testing. > > Why this timeout is changed to 40ms not 50ms or 60ms? > What's the time we expected from SDM? > I hope we don't need to change this again. > > Thanks > Hao > > > > > > > Signed-off-by: Ang Tien Sung <tien.sung.ang@intel.com> > > > --- > > > drivers/fpga/altera-cvp.c | 2 +- > > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > > > diff --git a/drivers/fpga/altera-cvp.c b/drivers/fpga/altera-cvp.c > > > index 4ffb9da537d8..5295ff90482b 100644 > > > --- a/drivers/fpga/altera-cvp.c > > > +++ b/drivers/fpga/altera-cvp.c > > > @@ -52,7 +52,7 @@ > > > /* V2 Defines */ > > > #define VSE_CVP_TX_CREDITS 0x49 /* 8bit */ > > > > > > -#define V2_CREDIT_TIMEOUT_US 20000 > > > +#define V2_CREDIT_TIMEOUT_US 40000 > > > #define V2_CHECK_CREDIT_US 10 > > > #define V2_POLL_TIMEOUT_US 1000000 > > > #define V2_USER_TIMEOUT_US 500000 > > > > Acked-by: Xu Yilun <yilun.xu@intel.com> > > > > > -- > > > 2.25.1
diff --git a/drivers/fpga/altera-cvp.c b/drivers/fpga/altera-cvp.c index 4ffb9da537d8..5295ff90482b 100644 --- a/drivers/fpga/altera-cvp.c +++ b/drivers/fpga/altera-cvp.c @@ -52,7 +52,7 @@ /* V2 Defines */ #define VSE_CVP_TX_CREDITS 0x49 /* 8bit */ -#define V2_CREDIT_TIMEOUT_US 20000 +#define V2_CREDIT_TIMEOUT_US 40000 #define V2_CHECK_CREDIT_US 10 #define V2_POLL_TIMEOUT_US 1000000 #define V2_USER_TIMEOUT_US 500000