| Message ID | 20220315075753.8591-1-steven_lee@aspeedtech.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | hw: aspeed_scu: Add AST2600 hpll calculation function | expand |
On 3/15/22 08:57, Steven Lee wrote: > AST2600's HPLL register offset and bit definition are different from AST2500. > The patch series adds a hpll calculation function for ast2600 and modify apb frequency > calculation function based on SCU200 register description and note in ast2600v11.pdf. > > Changes since v1: > - introduce ast2400 and ast2600 get_apb_freq class handlers. > - introduce clkin_25Mhz attribute. > Looks good. They are queued for QEMU 7.1. Something I never had time to look at is the clock hierarchy in QEMU Aspeed machines : https://qemu.readthedocs.io/en/latest/devel/clocks.html It would be very useful to start the tree with clkin and the obvious derived clocks. Thanks, C. # cat /sys/kernel/debug/clk/clk_summary enable prepare protect duty hardware clock count count count rate accuracy phase cycle enable ------------------------------------------------------------------------------------------------------- fsiclk-gate 1 1 0 0 0 0 50000 Y i3cclk-gate 0 0 0 0 0 0 50000 N emmcclk-gate 1 1 0 0 0 0 50000 Y sdclk-gate 1 1 0 0 0 0 50000 Y rvasclk-gate 0 0 0 0 0 0 50000 N rsaclk-gate 0 0 0 0 0 0 50000 N usb-port2-gate 1 1 0 0 0 0 50000 Y usb-port1-gate 1 1 0 0 0 0 50000 Y usb-uhci-gate 1 1 0 0 0 0 50000 Y espiclk-gate 0 0 0 0 0 0 50000 N yclk-gate 0 0 0 0 0 0 50000 N lclk-gate 0 0 0 0 0 0 50000 N dclk-gate 1 1 0 0 0 0 50000 Y vclk-gate 0 0 0 0 0 0 50000 N gclk-gate 0 0 0 0 0 0 50000 N eclk 0 0 0 0 0 0 50000 Y eclk-gate 0 0 0 0 0 0 50000 N uartx 0 0 0 1846153 0 0 50000 Y uart13clk-gate 0 0 0 1846153 0 0 50000 N uart12clk-gate 0 0 0 1846153 0 0 50000 N uart11clk-gate 0 0 0 1846153 0 0 50000 N uart10clk-gate 0 0 0 1846153 0 0 50000 N uart9clk-gate 0 0 0 1846153 0 0 50000 N uart8clk-gate 0 0 0 1846153 0 0 50000 N uart7clk-gate 0 0 0 1846153 0 0 50000 N uart6clk-gate 0 0 0 1846153 0 0 50000 N uart 1 1 0 24000000 0 0 50000 Y uart5clk-gate 1 1 0 24000000 0 0 50000 Y uart4clk-gate 0 0 0 24000000 0 0 50000 N uart3clk-gate 0 0 0 24000000 0 0 50000 N uart2clk-gate 0 0 0 24000000 0 0 50000 N uart1clk-gate 0 0 0 24000000 0 0 50000 N usb-phy-40m 0 0 0 40000000 0 0 50000 Y clkin 4 4 0 25000000 0 0 50000 Y ref1clk-gate 1 1 0 25000000 0 0 50000 Y ref0clk-gate 1 1 0 25000000 0 0 50000 Y apll 0 0 0 800000000 0 0 50000 Y epll 0 0 0 1000000000 0 0 50000 Y dpll 0 0 0 50000000 0 0 50000 Y vclk 0 0 0 50000000 0 0 50000 Y mpll 2 2 0 400000000 0 0 50000 Y mclk-gate 1 1 0 400000000 0 0 50000 Y emmc_extclk_mux 1 1 0 400000000 0 0 50000 Y emmc_extclk_gate 1 1 0 400000000 0 0 50000 Y emmc_extclk 1 1 0 200000000 0 0 50000 Y hpll 4 4 0 1200000000 0 0 50000 Y bclk 1 1 0 150000000 0 0 50000 Y bclk-gate 1 1 0 150000000 0 0 50000 Y lhclk 0 0 0 150000000 0 0 50000 Y lhclk-gate 0 0 0 150000000 0 0 50000 N mac34 2 2 0 300000000 0 0 50000 Y mac4clk-gate 1 1 0 300000000 0 0 50000 Y mac3clk-gate 1 1 0 300000000 0 0 50000 Y mac12 2 2 0 200000000 0 0 50000 Y mac2clk-gate 1 1 0 200000000 0 0 50000 Y mac1clk-gate 1 1 0 200000000 0 0 50000 Y mac12rclk 0 0 0 50000000 0 0 50000 Y mac2rclk 0 0 0 50000000 0 0 50000 N mac1rclk 0 0 0 50000000 0 0 50000 N sd_extclk_gate 0 0 0 1200000000 0 0 50000 N sd_extclk 0 0 0 150000000 0 0 50000 Y emmc_extclk_hpll_in 0 0 0 600000000 0 0 50000 Y apb1 0 0 0 37500000 0 0 50000 Y ahb 3 3 0 200000000 0 0 50000 Y i3cclk 0 0 0 200000000 0 0 50000 Y i3c6clk-gate 0 0 0 200000000 0 0 50000 N i3c5clk-gate 0 0 0 200000000 0 0 50000 N i3c4clk-gate 0 0 0 200000000 0 0 50000 N i3c3clk-gate 0 0 0 200000000 0 0 50000 N i3c2clk-gate 0 0 0 200000000 0 0 50000 N i3c1clk-gate 0 0 0 200000000 0 0 50000 N i3c0clk-gate 0 0 0 200000000 0 0 50000 N apb2 0 0 0 100000000 0 0 50000 Y d1clk 0 0 0 0 0 0 50000 Y d1clk-gate 0 0 0 0 0 0 50000 N mac34rclk 0 0 0 0 0 0 50000 Y mac4rclk 0 0 0 50000000 0 0 50000 N mac3rclk 0 0 0 50000000 0 0 50000 N