| Message ID | 20220314203845.832648-1-atishp@rivosinc.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | Provide a fraemework for RISC-V ISA extensions | expand |
On Mon, 14 Mar 2022 13:38:39 PDT (-0700), Atish Patra wrote: > This series implements a generic framework to parse multi-letter ISA > extensions. This series is based on Tsukasa's v3 isa extension improvement > series[1]. I have fixed few bugs and improved comments from that series > (PATCH1-3). I have not used PATCH 4 from that series as we are not using > ISA extension versioning as of now. We can add that later if required. > > PATCH 4 allows the probing of multi-letter extensions via a macro. > It continues to use the common isa extensions between all the harts. > Thus hetergenous hart systems will only see the common ISA extensions. > > PATCH 6 improves the /proc/cpuinfo interface for the available ISA extensions > via /proc/cpuinfo. > > Here is the example output of /proc/cpuinfo: > (with debug patches in Qemu and Linux kernel) > > / # cat /proc/cpuinfo > processor : 0 > hart : 0 > isa : rv64imafdch_svpbmt_svnapot_svinval > mmu : sv48 > > processor : 1 > hart : 1 > isa : rv64imafdch_svpbmt_svnapot_svinval > mmu : sv48 > > processor : 2 > hart : 2 > isa : rv64imafdch_svpbmt_svnapot_svinval > mmu : sv48 > > processor : 3 > hart : 3 > isa : rv64imafdch_svpbmt_svnapot_svinval > mmu : sv48 > > Anybody adding support for any new multi-letter extensions should add an > entry to the riscv_isa_ext_id and the isa extension array. > E.g. The patch[2] adds the support for various ISA extensions. > > [1] https://lore.kernel.org/all/0f568515-a05e-8204-aae3-035975af3ee8@irq.a4lg.com/T/ > [2] https://github.com/atishp04/linux/commit/e9e240c9a854dceb434ceb53bdbe82a657bee5f2 > > Changes from v5->v6: > 1. Changed the isa extension format from separate row to single row that follows > RISC-V spec naming standards. > > 2. Removed the redundant extension detection log. > > Changes from v4->v5: > 1. Improved the /proc/cpuinfo to include only valid & enabled extensions > 2. Improved the multi-letter parsing by skipping the 'su' modes generated in > Qemu as suggested by Tsukasa. > > Changes from v3->v4: > 1. Changed temporary variable for current hart isa to a bitmap > 2. Added reviewed-by tags. > 3. Improved comments > > Changes from v2->v3: > 1. Updated comments to mark clearly a fix required for Qemu only. > 2. Fixed a bug where the 1st multi-letter extension can be present without _ > 3. Added Tested by tags. > > Changes from v1->v2: > 1. Instead of adding a separate DT property use the riscv,isa property. > 2. Based on Tsukasa's v3 isa extension improvement series. > > Atish Patra (3): > RISC-V: Implement multi-letter ISA extension probing framework > RISC-V: Do no continue isa string parsing without correct XLEN > RISC-V: Improve /proc/cpuinfo output for ISA extensions > > Tsukasa OI (3): > RISC-V: Correctly print supported extensions > RISC-V: Minimal parser for "riscv, isa" strings > RISC-V: Extract multi-letter extension names from "riscv, isa" > > arch/riscv/include/asm/hwcap.h | 25 +++++++ > arch/riscv/kernel/cpu.c | 65 ++++++++++++++++- > arch/riscv/kernel/cpufeature.c | 128 +++++++++++++++++++++++++++------ > 3 files changed, 195 insertions(+), 23 deletions(-) Thanks, this is on for-next.