| Message ID | 20220301151238.15836-1-dinguyen@kernel.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | arm64: dts: n5x: add sdr edac support | expand |
On 01/03/2022 16:12, Dinh Nguyen wrote: > The N5X platform has the Synopsys DDR controller the includes an EDAC > controller. Add the entry for the controller in the DTS file instead of > the base Agilex DTSI because the base Agilex does not have the > controller. > > Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> > --- > arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts | 10 ++++++++++ > 1 file changed, 10 insertions(+) > > diff --git a/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts > index f3c1310dae0a..628c9943914b 100644 > --- a/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts > +++ b/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts > @@ -23,6 +23,16 @@ memory { > /* We expect the bootloader to fill in the reg */ > reg = <0 0 0 0>; > }; > + > + soc { > + sdram_edac: sdr_edac@f87f8000 { This patch was merged but it is not correct. The node name should be memory-controller (generic, not specific). > + compatible = "snps,ddrc-3.80a"; > + reg = <0xf87f8000 0x400>; > + interrupts = <0 175 4>; This fails dt schema. > + intel,sysmgr-syscon = <&sysmgr 0xb8>; This fails schema even more... it's not documented. > + status = "okay"; This is not needed. Please test your changes against bindings (you can use dtbs_check). Best regards, Krzysztof
On 3/18/22 07:00, Krzysztof Kozlowski wrote: > On 01/03/2022 16:12, Dinh Nguyen wrote: >> The N5X platform has the Synopsys DDR controller the includes an EDAC >> controller. Add the entry for the controller in the DTS file instead of >> the base Agilex DTSI because the base Agilex does not have the >> controller. >> >> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> >> --- >> arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts | 10 ++++++++++ >> 1 file changed, 10 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts >> index f3c1310dae0a..628c9943914b 100644 >> --- a/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts >> +++ b/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts >> @@ -23,6 +23,16 @@ memory { >> /* We expect the bootloader to fill in the reg */ >> reg = <0 0 0 0>; >> }; >> + >> + soc { >> + sdram_edac: sdr_edac@f87f8000 { > > This patch was merged but it is not correct. The node name should be > memory-controller (generic, not specific). > >> + compatible = "snps,ddrc-3.80a"; >> + reg = <0xf87f8000 0x400>; >> + interrupts = <0 175 4>; > > This fails dt schema. > >> + intel,sysmgr-syscon = <&sysmgr 0xb8>; > > This fails schema even more... it's not documented. > >> + status = "okay"; > > This is not needed. > > > Please test your changes against bindings (you can use dtbs_check). > Will do and I'll send a patch to fix this up in a bit. Thanks, Dinh
diff --git a/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts index f3c1310dae0a..628c9943914b 100644 --- a/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts +++ b/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts @@ -23,6 +23,16 @@ memory { /* We expect the bootloader to fill in the reg */ reg = <0 0 0 0>; }; + + soc { + sdram_edac: sdr_edac@f87f8000 { + compatible = "snps,ddrc-3.80a"; + reg = <0xf87f8000 0x400>; + interrupts = <0 175 4>; + intel,sysmgr-syscon = <&sysmgr 0xb8>; + status = "okay"; + }; + }; }; &clkmgr {
The N5X platform has the Synopsys DDR controller the includes an EDAC controller. Add the entry for the controller in the DTS file instead of the base Agilex DTSI because the base Agilex does not have the controller. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> --- arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts | 10 ++++++++++ 1 file changed, 10 insertions(+)