diff mbox series

[3/3] arm64: dts: agilex: use the compatible "intel,socfpga-agilex-hsotg"

Message ID 20220125161821.1951906-3-dinguyen@kernel.org (mailing list archive)
State Accepted
Commit 325b820fa97f40704439674421a55b443810938d
Headers show
Series [1/3] dt-bindings: usb: dwc2: add compatible "intel,socfpga-agilex-hsotg" | expand

Commit Message

Dinh Nguyen Jan. 25, 2022, 4:18 p.m. UTC 
The DWC2 USB controller on the Agilex platform does not support clock
gating, so use the chip specific "intel,socfpga-agilex-hsotg"
compatible.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
---
 arch/arm64/boot/dts/intel/socfpga_agilex.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

Comments

Krzysztof Kozlowski March 18, 2022, 2:34 p.m. UTC | #1 
On Tue, Jan 25, 2022 at 10:18:21AM -0600, Dinh Nguyen wrote:
> The DWC2 USB controller on the Agilex platform does not support clock
> gating, so use the chip specific "intel,socfpga-agilex-hsotg"
> compatible.
> 
> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
> ---
>  arch/arm64/boot/dts/intel/socfpga_agilex.dtsi | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
> index 0dd2d2ee765a..f4270cf18996 100644
> --- a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
> +++ b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
> @@ -502,7 +502,7 @@ uart1: serial@ffc02100 {
>  		};
>  
>  		usb0: usb@ffb00000 {
> -			compatible = "snps,dwc2";
> +			compatible = "intel,socfpga-agilex-hsotg", "snps,dwc2";

In the same patchset you sent a bindings change which is contradictory
to this DTS change.

This is wrong here and dtbs_check will complain.
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
index 0dd2d2ee765a..f4270cf18996 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
@@ -502,7 +502,7 @@  uart1: serial@ffc02100 {
 		};
 
 		usb0: usb@ffb00000 {
-			compatible = "snps,dwc2";
+			compatible = "intel,socfpga-agilex-hsotg", "snps,dwc2";
 			reg = <0xffb00000 0x40000>;
 			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 			phys = <&usbphy0>;
@@ -515,7 +515,7 @@  usb0: usb@ffb00000 {
 		};
 
 		usb1: usb@ffb40000 {
-			compatible = "snps,dwc2";
+			compatible = "intel,socfpga-agilex-hsotg", "snps,dwc2";
 			reg = <0xffb40000 0x40000>;
 			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 			phys = <&usbphy0>;