diff mbox series

ARM: spear: fix typos in comments

Message ID 20220318103729.157574-21-Julia.Lawall@inria.fr (mailing list archive)
State New, archived
Headers show
Series ARM: spear: fix typos in comments | expand

Commit Message

Julia Lawall March 18, 2022, 10:37 a.m. UTC
Various spelling mistakes in comments.
Detected with the help of Coccinelle.

Signed-off-by: Julia Lawall <Julia.Lawall@inria.fr>

---
 arch/arm/mach-spear/spear13xx.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Viresh Kumar March 21, 2022, 5:11 a.m. UTC | #1
On 18-03-22, 11:37, Julia Lawall wrote:
> Various spelling mistakes in comments.
> Detected with the help of Coccinelle.
> 
> Signed-off-by: Julia Lawall <Julia.Lawall@inria.fr>
> 
> ---
>  arch/arm/mach-spear/spear13xx.c |    2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm/mach-spear/spear13xx.c b/arch/arm/mach-spear/spear13xx.c
> index 74d1ca2a529a..b38391e9d8bf 100644
> --- a/arch/arm/mach-spear/spear13xx.c
> +++ b/arch/arm/mach-spear/spear13xx.c
> @@ -29,7 +29,7 @@ void __init spear13xx_l2x0_init(void)
>  	/*
>  	 * 512KB (64KB/way), 8-way associativity, parity supported
>  	 *
> -	 * FIXME: 9th bit, of Auxillary Controller register must be set
> +	 * FIXME: 9th bit, of Auxiliary Controller register must be set
>  	 * for some spear13xx devices for stable L2 operation.
>  	 *
>  	 * Enable Early BRESP, L2 prefetch for Instruction and Data,

Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
diff mbox series

Patch

diff --git a/arch/arm/mach-spear/spear13xx.c b/arch/arm/mach-spear/spear13xx.c
index 74d1ca2a529a..b38391e9d8bf 100644
--- a/arch/arm/mach-spear/spear13xx.c
+++ b/arch/arm/mach-spear/spear13xx.c
@@ -29,7 +29,7 @@  void __init spear13xx_l2x0_init(void)
 	/*
 	 * 512KB (64KB/way), 8-way associativity, parity supported
 	 *
-	 * FIXME: 9th bit, of Auxillary Controller register must be set
+	 * FIXME: 9th bit, of Auxiliary Controller register must be set
 	 * for some spear13xx devices for stable L2 operation.
 	 *
 	 * Enable Early BRESP, L2 prefetch for Instruction and Data,