diff mbox series

[1/2] drm: Add missing DP DSC extended capability definitions.

Message ID 20220321110305.12853-2-stanislav.lisovskiy@intel.com (mailing list archive)
State New, archived
Headers show
Series Add DP MST DSC support to i915 | expand

Commit Message

Stanislav Lisovskiy March 21, 2022, 11:03 a.m. UTC 
Adding DP DSC register definitions, we might need for further
DSC implementation, supporting MST and DP branch pass-through mode.

v2: - Fixed checkpatch comment warning

Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
 drivers/gpu/drm/dp/drm_dp.c    | 25 +++++++++++++++++++++++++
 include/drm/dp/drm_dp_helper.h | 11 ++++++++++-
 2 files changed, 35 insertions(+), 1 deletion(-)

Comments

Jani Nikula March 21, 2022, 12:44 p.m. UTC | #1 
On Mon, 21 Mar 2022, Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> wrote:
> Adding DP DSC register definitions, we might need for further
> DSC implementation, supporting MST and DP branch pass-through mode.
>
> v2: - Fixed checkpatch comment warning
>
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> ---
>  drivers/gpu/drm/dp/drm_dp.c    | 25 +++++++++++++++++++++++++
>  include/drm/dp/drm_dp_helper.h | 11 ++++++++++-
>  2 files changed, 35 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/dp/drm_dp.c b/drivers/gpu/drm/dp/drm_dp.c
> index 703972ae14c6..45815745ba7b 100644
> --- a/drivers/gpu/drm/dp/drm_dp.c
> +++ b/drivers/gpu/drm/dp/drm_dp.c
> @@ -2312,6 +2312,31 @@ u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
>  }
>  EXPORT_SYMBOL(drm_dp_dsc_sink_max_slice_count);
>  
> +/**
> + * drm_dp_dsc_sink_bpp_increment_div - Get the bits per pixel precision
> + * which DP DSC sink device supports.
> + */
> +u8 drm_dp_dsc_sink_bpp_increment_div(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
> +{
> +	u8 bpp_increment_dpcd = dsc_dpcd[DP_DSC_BITS_PER_PIXEL_INC - DP_DSC_SUPPORT];
> +
> +	switch (bpp_increment_dpcd) {

So I didn't look this up in the spec, but later in the patch you're
adding masks for the dpcd register in question, so I presume it's not
fine to assume the whole register is about bbp.

> +	case DP_DSC_BITS_PER_PIXEL_1_16:
> +		return 16;
> +	case DP_DSC_BITS_PER_PIXEL_1_8:
> +		return 8;
> +	case DP_DSC_BITS_PER_PIXEL_1_4:
> +		return 4;
> +	case DP_DSC_BITS_PER_PIXEL_1_2:
> +		return 2;
> +	case DP_DSC_BITS_PER_PIXEL_1_1:
> +		return 1;
> +	}
> +
> +	return 0;
> +}
> +
> +

Didn't checkpatch complain about the double newline?

You don't use the function for anything in patch 2. And you couldn't
because it's not exported to drivers.

BR,
Jani.

>  /**
>   * drm_dp_dsc_sink_line_buf_depth() - Get the line buffer depth in bits
>   * @dsc_dpcd: DSC capabilities from DPCD
> diff --git a/include/drm/dp/drm_dp_helper.h b/include/drm/dp/drm_dp_helper.h
> index 51e02cf75277..e4c9f4438ccb 100644
> --- a/include/drm/dp/drm_dp_helper.h
> +++ b/include/drm/dp/drm_dp_helper.h
> @@ -246,6 +246,9 @@ struct drm_panel;
>  
>  #define DP_DSC_SUPPORT                      0x060   /* DP 1.4 */
>  # define DP_DSC_DECOMPRESSION_IS_SUPPORTED  (1 << 0)
> +# define DP_DSC_PASS_THROUGH_IS_SUPPORTED   (1 << 1)
> +# define DP_DSC_DYNAMIC_PPS_UPDATE_SUPPORT_COMP_TO_COMP    (1 << 2)
> +# define DP_DSC_DYNAMIC_PPS_UPDATE_SUPPORT_UNCOMP_TO_COMP  (1 << 3)
>  
>  #define DP_DSC_REV                          0x061
>  # define DP_DSC_MAJOR_MASK                  (0xf << 0)
> @@ -284,12 +287,15 @@ struct drm_panel;
>  
>  #define DP_DSC_BLK_PREDICTION_SUPPORT       0x066
>  # define DP_DSC_BLK_PREDICTION_IS_SUPPORTED (1 << 0)
> +# define DP_DSC_RGB_COLOR_CONV_BYPASS_SUPPORT (1 << 1)
>  
>  #define DP_DSC_MAX_BITS_PER_PIXEL_LOW       0x067   /* eDP 1.4 */
>  
>  #define DP_DSC_MAX_BITS_PER_PIXEL_HI        0x068   /* eDP 1.4 */
>  # define DP_DSC_MAX_BITS_PER_PIXEL_HI_MASK  (0x3 << 0)
>  # define DP_DSC_MAX_BITS_PER_PIXEL_HI_SHIFT 8
> +# define DP_DSC_MAX_BPP_DELTA_VERSION_MASK  0x06
> +# define DP_DSC_MAX_BPP_DELTA_AVAILABILITY  0x08
>  
>  #define DP_DSC_DEC_COLOR_FORMAT_CAP         0x069
>  # define DP_DSC_RGB                         (1 << 0)
> @@ -351,11 +357,13 @@ struct drm_panel;
>  # define DP_DSC_24_PER_DP_DSC_SINK          (1 << 2)
>  
>  #define DP_DSC_BITS_PER_PIXEL_INC           0x06F
> +# define DP_DSC_RGB_YCbCr444_MAX_BPP_DELTA_MASK 0x1f
> +# define DP_DSC_RGB_YCbCr420_MAX_BPP_DELTA_MASK 0xe0
>  # define DP_DSC_BITS_PER_PIXEL_1_16         0x0
>  # define DP_DSC_BITS_PER_PIXEL_1_8          0x1
>  # define DP_DSC_BITS_PER_PIXEL_1_4          0x2
>  # define DP_DSC_BITS_PER_PIXEL_1_2          0x3
> -# define DP_DSC_BITS_PER_PIXEL_1            0x4
> +# define DP_DSC_BITS_PER_PIXEL_1_1          0x4
>  
>  #define DP_PSR_SUPPORT                      0x070   /* XXX 1.2? */
>  # define DP_PSR_IS_SUPPORTED                1
> @@ -1825,6 +1833,7 @@ u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
>  u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]);
>  int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpc[DP_DSC_RECEIVER_CAP_SIZE],
>  					 u8 dsc_bpc[3]);
> +u8 drm_dp_dsc_sink_bpp_increment_div(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]);
>  
>  static inline bool
>  drm_dp_sink_supports_dsc(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
Stanislav Lisovskiy March 21, 2022, 2:08 p.m. UTC | #2 
On Mon, Mar 21, 2022 at 02:44:20PM +0200, Jani Nikula wrote:
> On Mon, 21 Mar 2022, Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> wrote:
> > Adding DP DSC register definitions, we might need for further
> > DSC implementation, supporting MST and DP branch pass-through mode.
> >
> > v2: - Fixed checkpatch comment warning
> >
> > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > ---
> >  drivers/gpu/drm/dp/drm_dp.c    | 25 +++++++++++++++++++++++++
> >  include/drm/dp/drm_dp_helper.h | 11 ++++++++++-
> >  2 files changed, 35 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/dp/drm_dp.c b/drivers/gpu/drm/dp/drm_dp.c
> > index 703972ae14c6..45815745ba7b 100644
> > --- a/drivers/gpu/drm/dp/drm_dp.c
> > +++ b/drivers/gpu/drm/dp/drm_dp.c
> > @@ -2312,6 +2312,31 @@ u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
> >  }
> >  EXPORT_SYMBOL(drm_dp_dsc_sink_max_slice_count);
> >  
> > +/**
> > + * drm_dp_dsc_sink_bpp_increment_div - Get the bits per pixel precision
> > + * which DP DSC sink device supports.
> > + */
> > +u8 drm_dp_dsc_sink_bpp_increment_div(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
> > +{
> > +	u8 bpp_increment_dpcd = dsc_dpcd[DP_DSC_BITS_PER_PIXEL_INC - DP_DSC_SUPPORT];
> > +
> > +	switch (bpp_increment_dpcd) {
> 
> So I didn't look this up in the spec, but later in the patch you're
> adding masks for the dpcd register in question, so I presume it's not
> fine to assume the whole register is about bbp.

In spec its called MAX_BPP_DELTA_AND_MAX_BPP_INCREMENT, for DP 1.4
rest bits are reserved, except those for bpp increment, while in
DP 2.0, rest are for max bpp delta(table 2-183)
I thought that full name would be too long and also confusing.

> 
> > +	case DP_DSC_BITS_PER_PIXEL_1_16:
> > +		return 16;
> > +	case DP_DSC_BITS_PER_PIXEL_1_8:
> > +		return 8;
> > +	case DP_DSC_BITS_PER_PIXEL_1_4:
> > +		return 4;
> > +	case DP_DSC_BITS_PER_PIXEL_1_2:
> > +		return 2;
> > +	case DP_DSC_BITS_PER_PIXEL_1_1:
> > +		return 1;
> > +	}
> > +
> > +	return 0;
> > +}
> > +
> > +
> 
> Didn't checkpatch complain about the double newline?

Actually it did. Fixed rest of warns, but for some reason didn't
spot this one.

> 
> You don't use the function for anything in patch 2. And you couldn't
> because it's not exported to drivers.

Yes, I think we don't support currently those increments, but I guess 
we will need those in future. Should I remove it until we actually start
using them?


Stan

> 
> BR,
> Jani.
> 
> >  /**
> >   * drm_dp_dsc_sink_line_buf_depth() - Get the line buffer depth in bits
> >   * @dsc_dpcd: DSC capabilities from DPCD
> > diff --git a/include/drm/dp/drm_dp_helper.h b/include/drm/dp/drm_dp_helper.h
> > index 51e02cf75277..e4c9f4438ccb 100644
> > --- a/include/drm/dp/drm_dp_helper.h
> > +++ b/include/drm/dp/drm_dp_helper.h
> > @@ -246,6 +246,9 @@ struct drm_panel;
> >  
> >  #define DP_DSC_SUPPORT                      0x060   /* DP 1.4 */
> >  # define DP_DSC_DECOMPRESSION_IS_SUPPORTED  (1 << 0)
> > +# define DP_DSC_PASS_THROUGH_IS_SUPPORTED   (1 << 1)
> > +# define DP_DSC_DYNAMIC_PPS_UPDATE_SUPPORT_COMP_TO_COMP    (1 << 2)
> > +# define DP_DSC_DYNAMIC_PPS_UPDATE_SUPPORT_UNCOMP_TO_COMP  (1 << 3)
> >  
> >  #define DP_DSC_REV                          0x061
> >  # define DP_DSC_MAJOR_MASK                  (0xf << 0)
> > @@ -284,12 +287,15 @@ struct drm_panel;
> >  
> >  #define DP_DSC_BLK_PREDICTION_SUPPORT       0x066
> >  # define DP_DSC_BLK_PREDICTION_IS_SUPPORTED (1 << 0)
> > +# define DP_DSC_RGB_COLOR_CONV_BYPASS_SUPPORT (1 << 1)
> >  
> >  #define DP_DSC_MAX_BITS_PER_PIXEL_LOW       0x067   /* eDP 1.4 */
> >  
> >  #define DP_DSC_MAX_BITS_PER_PIXEL_HI        0x068   /* eDP 1.4 */
> >  # define DP_DSC_MAX_BITS_PER_PIXEL_HI_MASK  (0x3 << 0)
> >  # define DP_DSC_MAX_BITS_PER_PIXEL_HI_SHIFT 8
> > +# define DP_DSC_MAX_BPP_DELTA_VERSION_MASK  0x06
> > +# define DP_DSC_MAX_BPP_DELTA_AVAILABILITY  0x08
> >  
> >  #define DP_DSC_DEC_COLOR_FORMAT_CAP         0x069
> >  # define DP_DSC_RGB                         (1 << 0)
> > @@ -351,11 +357,13 @@ struct drm_panel;
> >  # define DP_DSC_24_PER_DP_DSC_SINK          (1 << 2)
> >  
> >  #define DP_DSC_BITS_PER_PIXEL_INC           0x06F
> > +# define DP_DSC_RGB_YCbCr444_MAX_BPP_DELTA_MASK 0x1f
> > +# define DP_DSC_RGB_YCbCr420_MAX_BPP_DELTA_MASK 0xe0
> >  # define DP_DSC_BITS_PER_PIXEL_1_16         0x0
> >  # define DP_DSC_BITS_PER_PIXEL_1_8          0x1
> >  # define DP_DSC_BITS_PER_PIXEL_1_4          0x2
> >  # define DP_DSC_BITS_PER_PIXEL_1_2          0x3
> > -# define DP_DSC_BITS_PER_PIXEL_1            0x4
> > +# define DP_DSC_BITS_PER_PIXEL_1_1          0x4
> >  
> >  #define DP_PSR_SUPPORT                      0x070   /* XXX 1.2? */
> >  # define DP_PSR_IS_SUPPORTED                1
> > @@ -1825,6 +1833,7 @@ u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
> >  u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]);
> >  int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpc[DP_DSC_RECEIVER_CAP_SIZE],
> >  					 u8 dsc_bpc[3]);
> > +u8 drm_dp_dsc_sink_bpp_increment_div(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]);
> >  
> >  static inline bool
> >  drm_dp_sink_supports_dsc(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
> 
> -- 
> Jani Nikula, Intel Open Source Graphics Center
diff mbox series

Patch

diff --git a/drivers/gpu/drm/dp/drm_dp.c b/drivers/gpu/drm/dp/drm_dp.c
index 703972ae14c6..45815745ba7b 100644
--- a/drivers/gpu/drm/dp/drm_dp.c
+++ b/drivers/gpu/drm/dp/drm_dp.c
@@ -2312,6 +2312,31 @@  u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
 }
 EXPORT_SYMBOL(drm_dp_dsc_sink_max_slice_count);
 
+/**
+ * drm_dp_dsc_sink_bpp_increment_div - Get the bits per pixel precision
+ * which DP DSC sink device supports.
+ */
+u8 drm_dp_dsc_sink_bpp_increment_div(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
+{
+	u8 bpp_increment_dpcd = dsc_dpcd[DP_DSC_BITS_PER_PIXEL_INC - DP_DSC_SUPPORT];
+
+	switch (bpp_increment_dpcd) {
+	case DP_DSC_BITS_PER_PIXEL_1_16:
+		return 16;
+	case DP_DSC_BITS_PER_PIXEL_1_8:
+		return 8;
+	case DP_DSC_BITS_PER_PIXEL_1_4:
+		return 4;
+	case DP_DSC_BITS_PER_PIXEL_1_2:
+		return 2;
+	case DP_DSC_BITS_PER_PIXEL_1_1:
+		return 1;
+	}
+
+	return 0;
+}
+
+
 /**
  * drm_dp_dsc_sink_line_buf_depth() - Get the line buffer depth in bits
  * @dsc_dpcd: DSC capabilities from DPCD
diff --git a/include/drm/dp/drm_dp_helper.h b/include/drm/dp/drm_dp_helper.h
index 51e02cf75277..e4c9f4438ccb 100644
--- a/include/drm/dp/drm_dp_helper.h
+++ b/include/drm/dp/drm_dp_helper.h
@@ -246,6 +246,9 @@  struct drm_panel;
 
 #define DP_DSC_SUPPORT                      0x060   /* DP 1.4 */
 # define DP_DSC_DECOMPRESSION_IS_SUPPORTED  (1 << 0)
+# define DP_DSC_PASS_THROUGH_IS_SUPPORTED   (1 << 1)
+# define DP_DSC_DYNAMIC_PPS_UPDATE_SUPPORT_COMP_TO_COMP    (1 << 2)
+# define DP_DSC_DYNAMIC_PPS_UPDATE_SUPPORT_UNCOMP_TO_COMP  (1 << 3)
 
 #define DP_DSC_REV                          0x061
 # define DP_DSC_MAJOR_MASK                  (0xf << 0)
@@ -284,12 +287,15 @@  struct drm_panel;
 
 #define DP_DSC_BLK_PREDICTION_SUPPORT       0x066
 # define DP_DSC_BLK_PREDICTION_IS_SUPPORTED (1 << 0)
+# define DP_DSC_RGB_COLOR_CONV_BYPASS_SUPPORT (1 << 1)
 
 #define DP_DSC_MAX_BITS_PER_PIXEL_LOW       0x067   /* eDP 1.4 */
 
 #define DP_DSC_MAX_BITS_PER_PIXEL_HI        0x068   /* eDP 1.4 */
 # define DP_DSC_MAX_BITS_PER_PIXEL_HI_MASK  (0x3 << 0)
 # define DP_DSC_MAX_BITS_PER_PIXEL_HI_SHIFT 8
+# define DP_DSC_MAX_BPP_DELTA_VERSION_MASK  0x06
+# define DP_DSC_MAX_BPP_DELTA_AVAILABILITY  0x08
 
 #define DP_DSC_DEC_COLOR_FORMAT_CAP         0x069
 # define DP_DSC_RGB                         (1 << 0)
@@ -351,11 +357,13 @@  struct drm_panel;
 # define DP_DSC_24_PER_DP_DSC_SINK          (1 << 2)
 
 #define DP_DSC_BITS_PER_PIXEL_INC           0x06F
+# define DP_DSC_RGB_YCbCr444_MAX_BPP_DELTA_MASK 0x1f
+# define DP_DSC_RGB_YCbCr420_MAX_BPP_DELTA_MASK 0xe0
 # define DP_DSC_BITS_PER_PIXEL_1_16         0x0
 # define DP_DSC_BITS_PER_PIXEL_1_8          0x1
 # define DP_DSC_BITS_PER_PIXEL_1_4          0x2
 # define DP_DSC_BITS_PER_PIXEL_1_2          0x3
-# define DP_DSC_BITS_PER_PIXEL_1            0x4
+# define DP_DSC_BITS_PER_PIXEL_1_1          0x4
 
 #define DP_PSR_SUPPORT                      0x070   /* XXX 1.2? */
 # define DP_PSR_IS_SUPPORTED                1
@@ -1825,6 +1833,7 @@  u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
 u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]);
 int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpc[DP_DSC_RECEIVER_CAP_SIZE],
 					 u8 dsc_bpc[3]);
+u8 drm_dp_dsc_sink_bpp_increment_div(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]);
 
 static inline bool
 drm_dp_sink_supports_dsc(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])