| Message ID | 20220317082230.23622-4-irui.wang@mediatek.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Enable two H264 encoder core on MT8195 | expand |
Hi Irui, > + > +%YAML 1.2 > +--- > +$id: "http://devicetree.org/schemas/media/mediatek,vcodec-encoder-core.yaml#" > +$schema: "http://devicetree.org/meta-schemas/core.yaml#" > + > +title: Mediatek Video Encoder Accelerator With Multi Core s/Mediatek/MediaTek/ > + > +maintainers: > + - Irui Wang <irui.wang@mediatek.com> > + > +description: | > + Mediatek Video Encode is the video encode hardware present in Mediatek s/Mediatek/MediaTek/ > + SoCs which supports high resolution encoding functionalities. Required > + parent and child device node. > + Thanks, Miles
On Thu, Mar 17, 2022 at 04:22:23PM +0800, Irui Wang wrote: > Adds encoder cores dt-bindings for mt8195. Why? > > Signed-off-by: Irui Wang <irui.wang@mediatek.com> > --- > .../media/mediatek,vcodec-encoder-core.yaml | 181 ++++++++++++++++++ > .../media/mediatek,vcodec-encoder.yaml | 1 - > 2 files changed, 181 insertions(+), 1 deletion(-) > create mode 100644 Documentation/devicetree/bindings/media/mediatek,vcodec-encoder-core.yaml > > diff --git a/Documentation/devicetree/bindings/media/mediatek,vcodec-encoder-core.yaml b/Documentation/devicetree/bindings/media/mediatek,vcodec-encoder-core.yaml > new file mode 100644 > index 000000000000..fcfb48900c76 > --- /dev/null > +++ b/Documentation/devicetree/bindings/media/mediatek,vcodec-encoder-core.yaml > @@ -0,0 +1,181 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > + > +%YAML 1.2 > +--- > +$id: "http://devicetree.org/schemas/media/mediatek,vcodec-encoder-core.yaml#" > +$schema: "http://devicetree.org/meta-schemas/core.yaml#" > + > +title: Mediatek Video Encoder Accelerator With Multi Core > + > +maintainers: > + - Irui Wang <irui.wang@mediatek.com> > + > +description: | > + Mediatek Video Encode is the video encode hardware present in Mediatek > + SoCs which supports high resolution encoding functionalities. Required > + parent and child device node. > + > +properties: > + compatible: > + items: > + - enum: > + - mediatek,mt8195-vcodec-enc > + > + mediatek,scp: > + $ref: /schemas/types.yaml#/definitions/phandle > + description: | > + The node of system control processor (SCP), using > + the remoteproc & rpmsg framework. > + > + mediatek,venc-multi-core: > + type: boolean > + description: | > + Indicates whether the encoder has multiple cores or not. Isn't this implied by how many child nodes you have? > + > + iommus: > + minItems: 1 > + maxItems: 32 You really have up to 32 IOMMUs? > + description: | > + List of the hardware port in respective IOMMU block for current Socs. > + Refer to bindings/iommu/mediatek,iommu.yaml. > + > + dma-ranges: > + maxItems: 1 > + description: | > + Describes the physical address space of IOMMU maps to memory. > + > + "#address-cells": > + const: 2 > + > + "#size-cells": > + const: 2 > + > + ranges: true > + > +# Required child node: > +patternProperties: > + "^venc-core@[0-9a-f]+$": > + type: object > + description: | > + The video encoder core device node which should be added as subnodes to > + the main venc node. > + > + properties: > + compatible: > + items: > + - const: mediatek,mtk-venc-core > + > + reg: > + maxItems: 1 > + > + mediatek,core-id: > + $ref: /schemas/types.yaml#/definitions/uint32 > + description: | > + Current encoder core id. What is this for and what does its value correspond to in the h/w. We generally don't do made up indices in DT. > + > + iommus: > + minItems: 1 > + maxItems: 32 > + description: | > + List of the hardware port in respective IOMMU block for current Socs. > + Refer to bindings/iommu/mediatek,iommu.yaml. > + > + interrupts: > + maxItems: 1 > + > + clocks: > + maxItems: 1 > + > + clock-names: > + maxItems: 1 > + > + power-domains: > + maxItems: 1 > + > + required: > + - compatible > + - reg > + - mediatek,core-id > + - iommus > + - interrupts > + - clocks > + - clock-names > + - assigned-clocks > + - assigned-clock-parents > + - power-domains > + > + additionalProperties: false > + > +required: > + - compatible > + - mediatek,scp > + - iommus > + - dma-ranges > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + #include <dt-bindings/memory/mt8195-memory-port.h> > + #include <dt-bindings/interrupt-controller/irq.h> > + #include <dt-bindings/clock/mt8195-clk.h> > + #include <dt-bindings/power/mt8195-power.h> > + > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + > + venc { > + compatible = "mediatek,mt8195-vcodec-enc"; > + mediatek,scp = <&scp>; > + mediatek,venc-multi-core; > + iommus = <&iommu_vdo M4U_PORT_L19_VENC_RCPU>; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>; > + > + venc-core@1a020000 { > + compatible = "mediatek,mtk-venc-core"; > + reg = <0 0x1a020000 0 0x10000>; > + mediatek,core-id = <0>; > + iommus = <&iommu_vdo M4U_PORT_L19_VENC_RCPU>, > + <&iommu_vdo M4U_PORT_L19_VENC_REC>, > + <&iommu_vdo M4U_PORT_L19_VENC_BSDMA>, > + <&iommu_vdo M4U_PORT_L19_VENC_SV_COMV>, > + <&iommu_vdo M4U_PORT_L19_VENC_RD_COMV>, > + <&iommu_vdo M4U_PORT_L19_VENC_CUR_LUMA>, > + <&iommu_vdo M4U_PORT_L19_VENC_CUR_CHROMA>, > + <&iommu_vdo M4U_PORT_L19_VENC_REF_LUMA>, > + <&iommu_vdo M4U_PORT_L19_VENC_REF_CHROMA>; > + interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH 0>; > + clocks = <&vencsys CLK_VENC_VENC>; > + clock-names = "clk_venc"; > + assigned-clocks = <&topckgen CLK_TOP_VENC>; > + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>; > + power-domains = <&spm MT8195_POWER_DOMAIN_VENC>; > + }; > + > + venc-core@1b020000 { > + compatible = "mediatek,mtk-venc-core"; > + reg = <0 0x1b020000 0 0x10000>; > + mediatek,core-id = <1>; > + iommus = <&iommu_vpp M4U_PORT_L20_VENC_RCPU>, > + <&iommu_vpp M4U_PORT_L20_VENC_REC>, > + <&iommu_vpp M4U_PORT_L20_VENC_BSDMA>, > + <&iommu_vpp M4U_PORT_L20_VENC_SV_COMV>, > + <&iommu_vpp M4U_PORT_L20_VENC_RD_COMV>, > + <&iommu_vpp M4U_PORT_L20_VENC_CUR_LUMA>, > + <&iommu_vpp M4U_PORT_L20_VENC_CUR_CHROMA>, > + <&iommu_vpp M4U_PORT_L20_VENC_REF_LUMA>, > + <&iommu_vpp M4U_PORT_L20_VENC_REF_CHROMA>; > + interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH 0>; > + clocks = <&vencsys_core1 CLK_VENC_CORE1_VENC>; > + clock-names = "clk_venc_core1"; > + assigned-clocks = <&topckgen CLK_TOP_VENC>; > + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>; > + power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>; > + }; > + }; > + }; > diff --git a/Documentation/devicetree/bindings/media/mediatek,vcodec-encoder.yaml b/Documentation/devicetree/bindings/media/mediatek,vcodec-encoder.yaml > index e7b65a91c92c..0530a694bcbe 100644 > --- a/Documentation/devicetree/bindings/media/mediatek,vcodec-encoder.yaml > +++ b/Documentation/devicetree/bindings/media/mediatek,vcodec-encoder.yaml > @@ -21,7 +21,6 @@ properties: > - mediatek,mt8173-vcodec-enc > - mediatek,mt8183-vcodec-enc > - mediatek,mt8192-vcodec-enc > - - mediatek,mt8195-vcodec-enc > > reg: > maxItems: 1 > -- > 2.18.0 > >
Dear Rob, Thanks for your review and comments. On Fri, 2022-03-25 at 15:57 -0500, Rob Herring wrote: > On Thu, Mar 17, 2022 at 04:22:23PM +0800, Irui Wang wrote: > > Adds encoder cores dt-bindings for mt8195. > > Why? mt8195 has two h264 encoder cores and we want to enable both of them. the original encoder bindings file is for single core which may can not handle it, so we new a core dt-bindings. We will think about it again about this dt-bindings. > > > > > Signed-off-by: Irui Wang <irui.wang@mediatek.com> > > --- > > .../media/mediatek,vcodec-encoder-core.yaml | 181 > > ++++++++++++++++++ > > .../media/mediatek,vcodec-encoder.yaml | 1 - > > 2 files changed, 181 insertions(+), 1 deletion(-) > > create mode 100644 > > Documentation/devicetree/bindings/media/mediatek,vcodec-encoder- > > core.yaml > > > > diff --git > > a/Documentation/devicetree/bindings/media/mediatek,vcodec-encoder- > > core.yaml > > b/Documentation/devicetree/bindings/media/mediatek,vcodec-encoder- > > core.yaml > > new file mode 100644 > > index 000000000000..fcfb48900c76 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/media/mediatek,vcodec- > > encoder-core.yaml > > @@ -0,0 +1,181 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > + > > +%YAML 1.2 > > +--- > > +$id: " > > http://devicetree.org/schemas/media/mediatek,vcodec-encoder-core.yaml# > > " > > +$schema: "http://devicetree.org/meta-schemas/core.yaml#" > > + > > +title: Mediatek Video Encoder Accelerator With Multi Core > > + > > +maintainers: > > + - Irui Wang <irui.wang@mediatek.com> > > + > > +description: | > > + Mediatek Video Encode is the video encode hardware present in > > Mediatek > > + SoCs which supports high resolution encoding functionalities. > > Required > > + parent and child device node. > > + > > +properties: > > + compatible: > > + items: > > + - enum: > > + - mediatek,mt8195-vcodec-enc > > + > > + mediatek,scp: > > + $ref: /schemas/types.yaml#/definitions/phandle > > + description: | > > + The node of system control processor (SCP), using > > + the remoteproc & rpmsg framework. > > + > > + mediatek,venc-multi-core: > > + type: boolean > > + description: | > > + Indicates whether the encoder has multiple cores or not. > > Isn't this implied by how many child nodes you have? It implies that we have child nodes, distinguish with single core, > > > + > > + iommus: > > + minItems: 1 > > + maxItems: 32 > > You really have up to 32 IOMMUs? Currently, totally 27 IOMMUs and used 9 of them. > > > + description: | > > + List of the hardware port in respective IOMMU block for > > current Socs. > > + Refer to bindings/iommu/mediatek,iommu.yaml. > > + > > + dma-ranges: > > + maxItems: 1 > > + description: | > > + Describes the physical address space of IOMMU maps to > > memory. > > + > > + "#address-cells": > > + const: 2 > > + > > + "#size-cells": > > + const: 2 > > + > > + ranges: true > > + > > +# Required child node: > > +patternProperties: > > + "^venc-core@[0-9a-f]+$": > > + type: object > > + description: | > > + The video encoder core device node which should be added as > > subnodes to > > + the main venc node. > > + > > + properties: > > + compatible: > > + items: > > + - const: mediatek,mtk-venc-core > > + > > + reg: > > + maxItems: 1 > > + > > + mediatek,core-id: > > + $ref: /schemas/types.yaml#/definitions/uint32 > > + description: | > > + Current encoder core id. > > What is this for and what does its value correspond to in the h/w. > We > generally don't do made up indices in DT. It's for encoder core id, core@1a020000 must be core-0, core@1b020000 must be core-1, we add this property in each child node, so we can get core-id in drivers. If it can't ref "uint32" types yaml, would you mind giving some more suggestions ? > > > + > > + iommus: > > + minItems: 1 > > + maxItems: 32 > > + description: | > > + List of the hardware port in respective IOMMU block for > > current Socs. > > + Refer to bindings/iommu/mediatek,iommu.yaml. > > + > > + interrupts: > > + maxItems: 1 > > + > > + clocks: > > + maxItems: 1 > > + > > + clock-names: > > + maxItems: 1 > > + > > + power-domains: > > + maxItems: 1 > > + > > + required: > > + - compatible > > + - reg > > + - mediatek,core-id > > + - iommus > > + - interrupts > > + - clocks > > + - clock-names > > + - assigned-clocks > > + - assigned-clock-parents > > + - power-domains > > + > > + additionalProperties: false > > + > > +required: > > + - compatible > > + - mediatek,scp > > + - iommus > > + - dma-ranges > > + > > +additionalProperties: false > > + > > +examples: > > + - | > > + #include <dt-bindings/interrupt-controller/arm-gic.h> > > + #include <dt-bindings/memory/mt8195-memory-port.h> > > + #include <dt-bindings/interrupt-controller/irq.h> > > + #include <dt-bindings/clock/mt8195-clk.h> > > + #include <dt-bindings/power/mt8195-power.h> > > + > > + soc { > > + #address-cells = <2>; > > + #size-cells = <2>; > > + > > + venc { > > + compatible = "mediatek,mt8195-vcodec-enc"; > > + mediatek,scp = <&scp>; > > + mediatek,venc-multi-core; > > + iommus = <&iommu_vdo M4U_PORT_L19_VENC_RCPU>; > > + #address-cells = <2>; > > + #size-cells = <2>; > > + ranges; > > + dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>; > > + > > + venc-core@1a020000 { > > + compatible = "mediatek,mtk-venc-core"; > > + reg = <0 0x1a020000 0 0x10000>; > > + mediatek,core-id = <0>; > > + iommus = <&iommu_vdo M4U_PORT_L19_VENC_RCPU>, > > + <&iommu_vdo M4U_PORT_L19_VENC_REC>, > > + <&iommu_vdo M4U_PORT_L19_VENC_BSDMA>, > > + <&iommu_vdo M4U_PORT_L19_VENC_SV_COMV>, > > + <&iommu_vdo M4U_PORT_L19_VENC_RD_COMV>, > > + <&iommu_vdo M4U_PORT_L19_VENC_CUR_LUMA>, > > + <&iommu_vdo > > M4U_PORT_L19_VENC_CUR_CHROMA>, > > + <&iommu_vdo M4U_PORT_L19_VENC_REF_LUMA>, > > + <&iommu_vdo > > M4U_PORT_L19_VENC_REF_CHROMA>; > > + interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH 0>; > > + clocks = <&vencsys CLK_VENC_VENC>; > > + clock-names = "clk_venc"; > > + assigned-clocks = <&topckgen CLK_TOP_VENC>; > > + assigned-clock-parents = <&topckgen > > CLK_TOP_UNIVPLL_D4>; > > + power-domains = <&spm MT8195_POWER_DOMAIN_VENC>; > > + }; > > + > > + venc-core@1b020000 { > > + compatible = "mediatek,mtk-venc-core"; > > + reg = <0 0x1b020000 0 0x10000>; > > + mediatek,core-id = <1>; > > + iommus = <&iommu_vpp M4U_PORT_L20_VENC_RCPU>, > > + <&iommu_vpp M4U_PORT_L20_VENC_REC>, > > + <&iommu_vpp M4U_PORT_L20_VENC_BSDMA>, > > + <&iommu_vpp M4U_PORT_L20_VENC_SV_COMV>, > > + <&iommu_vpp M4U_PORT_L20_VENC_RD_COMV>, > > + <&iommu_vpp M4U_PORT_L20_VENC_CUR_LUMA>, > > + <&iommu_vpp > > M4U_PORT_L20_VENC_CUR_CHROMA>, > > + <&iommu_vpp M4U_PORT_L20_VENC_REF_LUMA>, > > + <&iommu_vpp > > M4U_PORT_L20_VENC_REF_CHROMA>; > > + interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH 0>; > > + clocks = <&vencsys_core1 CLK_VENC_CORE1_VENC>; > > + clock-names = "clk_venc_core1"; > > + assigned-clocks = <&topckgen CLK_TOP_VENC>; > > + assigned-clock-parents = <&topckgen > > CLK_TOP_UNIVPLL_D4>; > > + power-domains = <&spm > > MT8195_POWER_DOMAIN_VENC_CORE1>; > > + }; > > + }; > > + }; > > diff --git > > a/Documentation/devicetree/bindings/media/mediatek,vcodec- > > encoder.yaml > > b/Documentation/devicetree/bindings/media/mediatek,vcodec- > > encoder.yaml > > index e7b65a91c92c..0530a694bcbe 100644 > > --- a/Documentation/devicetree/bindings/media/mediatek,vcodec- > > encoder.yaml > > +++ b/Documentation/devicetree/bindings/media/mediatek,vcodec- > > encoder.yaml > > @@ -21,7 +21,6 @@ properties: > > - mediatek,mt8173-vcodec-enc > > - mediatek,mt8183-vcodec-enc > > - mediatek,mt8192-vcodec-enc > > - - mediatek,mt8195-vcodec-enc > > > > reg: > > maxItems: 1 > > -- > > 2.18.0 > > > > Thanks Best Regards
On Sat, Mar 26, 2022 at 10:00:55AM +0800, Irui Wang wrote: > Dear Rob, > > Thanks for your review and comments. > > On Fri, 2022-03-25 at 15:57 -0500, Rob Herring wrote: > > On Thu, Mar 17, 2022 at 04:22:23PM +0800, Irui Wang wrote: > > > Adds encoder cores dt-bindings for mt8195. > > > > Why? > mt8195 has two h264 encoder cores and we want to enable both of them. > the original encoder bindings file is for single core which may can not > handle it, so we new a core dt-bindings. We will think about it again > about this dt-bindings. > > > > > > > > Signed-off-by: Irui Wang <irui.wang@mediatek.com> > > > --- > > > .../media/mediatek,vcodec-encoder-core.yaml | 181 > > > ++++++++++++++++++ > > > .../media/mediatek,vcodec-encoder.yaml | 1 - > > > 2 files changed, 181 insertions(+), 1 deletion(-) > > > create mode 100644 > > > Documentation/devicetree/bindings/media/mediatek,vcodec-encoder- > > > core.yaml > > > > > > diff --git > > > a/Documentation/devicetree/bindings/media/mediatek,vcodec-encoder- > > > core.yaml > > > b/Documentation/devicetree/bindings/media/mediatek,vcodec-encoder- > > > core.yaml > > > new file mode 100644 > > > index 000000000000..fcfb48900c76 > > > --- /dev/null > > > +++ b/Documentation/devicetree/bindings/media/mediatek,vcodec- > > > encoder-core.yaml > > > @@ -0,0 +1,181 @@ > > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > > + > > > +%YAML 1.2 > > > +--- > > > +$id: " > > > http://devicetree.org/schemas/media/mediatek,vcodec-encoder-core.yaml# > > > " > > > +$schema: "http://devicetree.org/meta-schemas/core.yaml#" > > > + > > > +title: Mediatek Video Encoder Accelerator With Multi Core > > > + > > > +maintainers: > > > + - Irui Wang <irui.wang@mediatek.com> > > > + > > > +description: | > > > + Mediatek Video Encode is the video encode hardware present in > > > Mediatek > > > + SoCs which supports high resolution encoding functionalities. > > > Required > > > + parent and child device node. > > > + > > > +properties: > > > + compatible: > > > + items: > > > + - enum: > > > + - mediatek,mt8195-vcodec-enc > > > + > > > + mediatek,scp: > > > + $ref: /schemas/types.yaml#/definitions/phandle > > > + description: | > > > + The node of system control processor (SCP), using > > > + the remoteproc & rpmsg framework. > > > + > > > + mediatek,venc-multi-core: > > > + type: boolean > > > + description: | > > > + Indicates whether the encoder has multiple cores or not. > > > > Isn't this implied by how many child nodes you have? > It implies that we have child nodes, distinguish with single core, Just check if you have a child node or not. > > > + iommus: > > > + minItems: 1 > > > + maxItems: 32 > > > > You really have up to 32 IOMMUs? > Currently, totally 27 IOMMUs and used 9 of them. > > > > > + description: | > > > + List of the hardware port in respective IOMMU block for > > > current Socs. > > > + Refer to bindings/iommu/mediatek,iommu.yaml. > > > + > > > + dma-ranges: > > > + maxItems: 1 > > > + description: | > > > + Describes the physical address space of IOMMU maps to > > > memory. > > > + > > > + "#address-cells": > > > + const: 2 > > > + > > > + "#size-cells": > > > + const: 2 > > > + > > > + ranges: true > > > + > > > +# Required child node: > > > +patternProperties: > > > + "^venc-core@[0-9a-f]+$": > > > + type: object > > > + description: | > > > + The video encoder core device node which should be added as > > > subnodes to > > > + the main venc node. > > > + > > > + properties: > > > + compatible: > > > + items: > > > + - const: mediatek,mtk-venc-core > > > + > > > + reg: > > > + maxItems: 1 > > > + > > > + mediatek,core-id: > > > + $ref: /schemas/types.yaml#/definitions/uint32 > > > + description: | > > > + Current encoder core id. > > > > What is this for and what does its value correspond to in the h/w. > > We > > generally don't do made up indices in DT. > It's for encoder core id, core@1a020000 must be core-0, core@1b020000 > must be core-1, we add this property in each child node, so we can > get core-id in drivers. If it can't ref "uint32" types yaml, would > you mind giving some more suggestions ? I still don't understand why it is needed. What is 'core-0'? Is there some functional difference between the cores? If so, describe that difference. Rob
Dear Rob, Many thanks for your attention. On Mon, 2022-03-28 at 08:48 -0500, Rob Herring wrote: > On Sat, Mar 26, 2022 at 10:00:55AM +0800, Irui Wang wrote: > > Dear Rob, > > > > Thanks for your review and comments. > > > > On Fri, 2022-03-25 at 15:57 -0500, Rob Herring wrote: > > > On Thu, Mar 17, 2022 at 04:22:23PM +0800, Irui Wang wrote: > > > > Adds encoder cores dt-bindings for mt8195. > > > > > > Why? > > > > mt8195 has two h264 encoder cores and we want to enable both of > > them. > > the original encoder bindings file is for single core which may can > > not > > handle it, so we new a core dt-bindings. We will think about it > > again > > about this dt-bindings. > > > > > > > > > > > Signed-off-by: Irui Wang <irui.wang@mediatek.com> > > > > --- > > > > .../media/mediatek,vcodec-encoder-core.yaml | 181 > > > > ++++++++++++++++++ > > > > .../media/mediatek,vcodec-encoder.yaml | 1 - > > > > 2 files changed, 181 insertions(+), 1 deletion(-) > > > > create mode 100644 > > > > Documentation/devicetree/bindings/media/mediatek,vcodec- > > > > encoder- > > > > core.yaml > > > > > > > > diff --git > > > > a/Documentation/devicetree/bindings/media/mediatek,vcodec- > > > > encoder- > > > > core.yaml > > > > b/Documentation/devicetree/bindings/media/mediatek,vcodec- > > > > encoder- > > > > core.yaml > > > > new file mode 100644 > > > > index 000000000000..fcfb48900c76 > > > > --- /dev/null > > > > +++ b/Documentation/devicetree/bindings/media/mediatek,vcodec- > > > > encoder-core.yaml > > > > @@ -0,0 +1,181 @@ > > > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > > > + > > > > +%YAML 1.2 > > > > +--- > > > > +$id: " > > > > http://devicetree.org/schemas/media/mediatek,vcodec-encoder-core.yaml# > > > > " > > > > +$schema: "http://devicetree.org/meta-schemas/core.yaml#" > > > > + > > > > +title: Mediatek Video Encoder Accelerator With Multi Core > > > > + > > > > +maintainers: > > > > + - Irui Wang <irui.wang@mediatek.com> > > > > + > > > > +description: | > > > > + Mediatek Video Encode is the video encode hardware present > > > > in > > > > Mediatek > > > > + SoCs which supports high resolution encoding > > > > functionalities. > > > > Required > > > > + parent and child device node. > > > > + > > > > +properties: > > > > + compatible: > > > > + items: > > > > + - enum: > > > > + - mediatek,mt8195-vcodec-enc > > > > + > > > > + mediatek,scp: > > > > + $ref: /schemas/types.yaml#/definitions/phandle > > > > + description: | > > > > + The node of system control processor (SCP), using > > > > + the remoteproc & rpmsg framework. > > > > + > > > > + mediatek,venc-multi-core: > > > > + type: boolean > > > > + description: | > > > > + Indicates whether the encoder has multiple cores or not. > > > > > > Isn't this implied by how many child nodes you have? > > > > It implies that we have child nodes, distinguish with single > > core, > > Just check if you have a child node or not. Yes. > > > > > > + iommus: > > > > + minItems: 1 > > > > + maxItems: 32 > > > > > > You really have up to 32 IOMMUs? > > > > Currently, totally 27 IOMMUs and used 9 of them. > > > > > > > + description: | > > > > + List of the hardware port in respective IOMMU block for > > > > current Socs. > > > > + Refer to bindings/iommu/mediatek,iommu.yaml. > > > > + > > > > + dma-ranges: > > > > + maxItems: 1 > > > > + description: | > > > > + Describes the physical address space of IOMMU maps to > > > > memory. > > > > + > > > > + "#address-cells": > > > > + const: 2 > > > > + > > > > + "#size-cells": > > > > + const: 2 > > > > + > > > > + ranges: true > > > > + > > > > +# Required child node: > > > > +patternProperties: > > > > + "^venc-core@[0-9a-f]+$": > > > > + type: object > > > > + description: | > > > > + The video encoder core device node which should be added > > > > as > > > > subnodes to > > > > + the main venc node. > > > > + > > > > + properties: > > > > + compatible: > > > > + items: > > > > + - const: mediatek,mtk-venc-core > > > > + > > > > + reg: > > > > + maxItems: 1 > > > > + > > > > + mediatek,core-id: > > > > + $ref: /schemas/types.yaml#/definitions/uint32 > > > > + description: | > > > > + Current encoder core id. > > > > > > What is this for and what does its value correspond to in the > > > h/w. > > > We > > > generally don't do made up indices in DT. > > > > It's for encoder core id, core@1a020000 must be core-0, > > core@1b020000 > > must be core-1, we add this property in each child node, so we can > > get core-id in drivers. If it can't ref "uint32" types yaml, would > > you mind giving some more suggestions ? > > I still don't understand why it is needed. What is 'core-0'? > > Is there some functional difference between the cores? If so, > describe > that difference. > > Rob They are two different pieces of hardware, it's our encoder hardware design. There are two encoder hardware cores inside MT8195, named core0 and core1(we can rename it, but core id should be declared), for core0, its module base address is 0x1A02_0000, uses IOMMU "vdo0_iommu" and power domain "POWER_DOMAIN_VENC", for core1, its module base address is 0x1B02_0000, uses IOMMU "vpp_iommu" and power domain "POWER_DOMAIN_VENC_CORE1". So the two encoder cores have their own base, IRQ, clock, power, etc. Each core can encode independently, moreover, they can work together for higher performance. We will describe more details in YAML about it if it's OK for you. Thanks Best Regards.
On Tue, Mar 29, 2022 at 09:26:37AM +0800, Irui Wang wrote: > Dear Rob, > > Many thanks for your attention. > > On Mon, 2022-03-28 at 08:48 -0500, Rob Herring wrote: > > On Sat, Mar 26, 2022 at 10:00:55AM +0800, Irui Wang wrote: > > > Dear Rob, > > > > > > Thanks for your review and comments. > > > > > > On Fri, 2022-03-25 at 15:57 -0500, Rob Herring wrote: > > > > On Thu, Mar 17, 2022 at 04:22:23PM +0800, Irui Wang wrote: > > > > > Adds encoder cores dt-bindings for mt8195. [...] > > > > > + mediatek,core-id: > > > > > + $ref: /schemas/types.yaml#/definitions/uint32 > > > > > + description: | > > > > > + Current encoder core id. > > > > > > > > What is this for and what does its value correspond to in the > > > > h/w. > > > > We > > > > generally don't do made up indices in DT. > > > > > > It's for encoder core id, core@1a020000 must be core-0, > > > core@1b020000 > > > must be core-1, we add this property in each child node, so we can > > > get core-id in drivers. If it can't ref "uint32" types yaml, would > > > you mind giving some more suggestions ? > > > > I still don't understand why it is needed. What is 'core-0'? > > > > Is there some functional difference between the cores? If so, > > describe > > that difference. > > > > Rob > > They are two different pieces of hardware, it's our encoder hardware > design. There are two encoder hardware cores inside MT8195, named core0 > and core1(we can rename it, but core id should be declared), > for core0, its module base address is 0x1A02_0000, uses IOMMU > "vdo0_iommu" and power domain "POWER_DOMAIN_VENC", > for core1, its module base address is 0x1B02_0000, uses IOMMU > "vpp_iommu" and power domain "POWER_DOMAIN_VENC_CORE1". > So the two encoder cores have their own base, IRQ, clock, power, etc. > Each core can encode independently, moreover, they can work together > for higher performance. > We will describe more details in YAML about it if it's OK for you. All the resources you list are in the child nodes, so you don't need 0 and 1 numbering for those. Looking at the driver patches, the only thing I see distinguishing core numbers is this: "frame#0 uses core#0, frame#1 uses core#1, frame#2 uses core#0..., Lock the device and enable the clock by used core, for sequence header encoding, it always uses core#0." Is this a requirement in the h/w or just what the driver picked? IOW, could frame#0 use core#1? Rob
Dear Rob, A sample encoder hardware block diagram attached. On Tue, 2022-03-29 at 08:09 -0500, Rob Herring wrote: > On Tue, Mar 29, 2022 at 09:26:37AM +0800, Irui Wang wrote: > > Dear Rob, > > > > Many thanks for your attention. > > > > On Mon, 2022-03-28 at 08:48 -0500, Rob Herring wrote: > > > On Sat, Mar 26, 2022 at 10:00:55AM +0800, Irui Wang wrote: > > > > Dear Rob, > > > > > > > > Thanks for your review and comments. > > > > > > > > On Fri, 2022-03-25 at 15:57 -0500, Rob Herring wrote: > > > > > On Thu, Mar 17, 2022 at 04:22:23PM +0800, Irui Wang wrote: > > > > > > Adds encoder cores dt-bindings for mt8195. > > [...] > > > > > > > + mediatek,core-id: > > > > > > + $ref: /schemas/types.yaml#/definitions/uint32 > > > > > > + description: | > > > > > > + Current encoder core id. > > > > > > > > > > What is this for and what does its value correspond to in the > > > > > h/w. > > > > > We > > > > > generally don't do made up indices in DT. > > > > > > > > It's for encoder core id, core@1a020000 must be core-0, > > > > core@1b020000 > > > > must be core-1, we add this property in each child node, so we > > > > can > > > > get core-id in drivers. If it can't ref "uint32" types yaml, > > > > would > > > > you mind giving some more suggestions ? > > > > > > I still don't understand why it is needed. What is 'core-0'? > > > > > > Is there some functional difference between the cores? If so, > > > describe > > > that difference. > > > > > > Rob > > > > They are two different pieces of hardware, it's our encoder > > hardware > > design. There are two encoder hardware cores inside MT8195, named > > core0 > > and core1(we can rename it, but core id should be declared), > > for core0, its module base address is 0x1A02_0000, uses IOMMU > > "vdo0_iommu" and power domain "POWER_DOMAIN_VENC", > > for core1, its module base address is 0x1B02_0000, uses IOMMU > > "vpp_iommu" and power domain "POWER_DOMAIN_VENC_CORE1". > > So the two encoder cores have their own base, IRQ, clock, power, > > etc. > > Each core can encode independently, moreover, they can work > > together > > for higher performance. > > We will describe more details in YAML about it if it's OK for you. > > All the resources you list are in the child nodes, so you don't need > 0 > and 1 numbering for those. > > Looking at the driver patches, the only thing I see distinguishing > core numbers is this: > > "frame#0 uses core#0, frame#1 uses core#1, frame#2 uses core#0..., > > Lock the device and enable the clock by used core, for sequence > header encoding, it always uses core#0." > > Is this a requirement in the h/w or just what the driver picked? > IOW, > could frame#0 use core#1? No, it's a requirement in the h/w, driver trigger core start encoding is in order. About the encoder hardware block diagram, please check below: -------------------------------------------------------------- Input Buffer: 0 1 2 3 4 5 6 | | | | | | | v | v | v | v +-------+ | +-------+ | +-------+ | +-------+ | core0 | | | core0 | | | core0 | | | core0 | +-------+ | +-------+ | +-------+ | +-------+ | | | | | | | | v | v | v | | +-------+ | +-------+ | +-------+ | | | core1 | | | core1 | | | core1 | | | +-------+ | +-------+ | +-------+ | | | | | | | | v v v v v v v <parent> -------------------------------------------------------------- core || index <child> \/ +-----------------------------------------------+ | core0/core1 | | enable/disable power/clk/irq | +-----------------------------------------------+ -------------------------------------------------------------- As above , there are parent and child devices, child mean each venc core, the child device controls the information of each core independent which inlcude power/clk/irq. When start encoding, input buffer 0 will be encoded by core0, and input buffer 1 can be encoded by core1 even if buffer 0 has not been encoded done yet, after buffer 0 encoded done, buffer 2 will be encoded by core0, and buffer 1 encoded done by core1. These two encoder cores will encode each input in this overlapping manner. We need manage each child device in parent device by core-id property. And we also need record current encoding input buffer, encode done output buffers and which one core is in used through core-id, because the two cores are encoding at the same time under one parent driver. > > Rob Thanks Best Regards
On Wed, Mar 30, 2022 at 04:48:47PM +0800, Irui Wang wrote: > Dear Rob, > > A sample encoder hardware block diagram attached. > On Tue, 2022-03-29 at 08:09 -0500, Rob Herring wrote: > > On Tue, Mar 29, 2022 at 09:26:37AM +0800, Irui Wang wrote: > > > Dear Rob, > > > > > > Many thanks for your attention. > > > > > > On Mon, 2022-03-28 at 08:48 -0500, Rob Herring wrote: > > > > On Sat, Mar 26, 2022 at 10:00:55AM +0800, Irui Wang wrote: > > > > > Dear Rob, > > > > > > > > > > Thanks for your review and comments. > > > > > > > > > > On Fri, 2022-03-25 at 15:57 -0500, Rob Herring wrote: > > > > > > On Thu, Mar 17, 2022 at 04:22:23PM +0800, Irui Wang wrote: > > > > > > > Adds encoder cores dt-bindings for mt8195. > > > > [...] > > > > > > > > > + mediatek,core-id: > > > > > > > + $ref: /schemas/types.yaml#/definitions/uint32 > > > > > > > + description: | > > > > > > > + Current encoder core id. > > > > > > > > > > > > What is this for and what does its value correspond to in the > > > > > > h/w. > > > > > > We > > > > > > generally don't do made up indices in DT. > > > > > > > > > > It's for encoder core id, core@1a020000 must be core-0, > > > > > core@1b020000 > > > > > must be core-1, we add this property in each child node, so we > > > > > can > > > > > get core-id in drivers. If it can't ref "uint32" types yaml, > > > > > would > > > > > you mind giving some more suggestions ? > > > > > > > > I still don't understand why it is needed. What is 'core-0'? > > > > > > > > Is there some functional difference between the cores? If so, > > > > describe > > > > that difference. > > > > > > > > Rob > > > > > > They are two different pieces of hardware, it's our encoder > > > hardware > > > design. There are two encoder hardware cores inside MT8195, named > > > core0 > > > and core1(we can rename it, but core id should be declared), > > > for core0, its module base address is 0x1A02_0000, uses IOMMU > > > "vdo0_iommu" and power domain "POWER_DOMAIN_VENC", > > > for core1, its module base address is 0x1B02_0000, uses IOMMU > > > "vpp_iommu" and power domain "POWER_DOMAIN_VENC_CORE1". > > > So the two encoder cores have their own base, IRQ, clock, power, > > > etc. > > > Each core can encode independently, moreover, they can work > > > together > > > for higher performance. > > > We will describe more details in YAML about it if it's OK for you. > > > > All the resources you list are in the child nodes, so you don't need > > 0 > > and 1 numbering for those. > > > > Looking at the driver patches, the only thing I see distinguishing > > core numbers is this: > > > > "frame#0 uses core#0, frame#1 uses core#1, frame#2 uses core#0..., > > > > Lock the device and enable the clock by used core, for sequence > > header encoding, it always uses core#0." > > > > Is this a requirement in the h/w or just what the driver picked? > > IOW, > > could frame#0 use core#1? > No, it's a requirement in the h/w, driver trigger core start encoding > is in order. > About the encoder hardware block diagram, please check below: > -------------------------------------------------------------- > Input Buffer: 0 1 2 3 4 5 6 > | | | | | | | > v | v | v | v > +-------+ | +-------+ | +-------+ | +-------+ > | core0 | | | core0 | | | core0 | | | core0 | > +-------+ | +-------+ | +-------+ | +-------+ > | | | | | | | > | v | v | v | > | +-------+ | +-------+ | +-------+ | > | | core1 | | | core1 | | | core1 | | > | +-------+ | +-------+ | +-------+ | > | | | | | | | > v v v v v v v <parent> > -------------------------------------------------------------- > core || index <child> > \/ > +-----------------------------------------------+ > | core0/core1 | > | enable/disable power/clk/irq | > +-----------------------------------------------+ > -------------------------------------------------------------- > As above , there are parent and child devices, child mean each venc > core, the child device controls the information of each core > independent which inlcude power/clk/irq. > When start encoding, input buffer 0 will be encoded by core0, and input > buffer 1 can be encoded by core1 even if buffer 0 has not been encoded > done yet, after buffer 0 encoded done, buffer 2 will be encoded by > core0, and buffer 1 encoded done by core1. These two encoder cores will > encode each input in this overlapping manner. > > We need manage each child device in parent device by core-id property. > And we also need record current encoding input buffer, encode done > output buffers and which one core is in used through core-id, because > the two cores are encoding at the same time under one parent driver. Okay, please summarize the h/w requirement in the property description. You might put the above diagram in the top description too. Rob
diff --git a/Documentation/devicetree/bindings/media/mediatek,vcodec-encoder-core.yaml b/Documentation/devicetree/bindings/media/mediatek,vcodec-encoder-core.yaml new file mode 100644 index 000000000000..fcfb48900c76 --- /dev/null +++ b/Documentation/devicetree/bindings/media/mediatek,vcodec-encoder-core.yaml @@ -0,0 +1,181 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) + +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/media/mediatek,vcodec-encoder-core.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Mediatek Video Encoder Accelerator With Multi Core + +maintainers: + - Irui Wang <irui.wang@mediatek.com> + +description: | + Mediatek Video Encode is the video encode hardware present in Mediatek + SoCs which supports high resolution encoding functionalities. Required + parent and child device node. + +properties: + compatible: + items: + - enum: + - mediatek,mt8195-vcodec-enc + + mediatek,scp: + $ref: /schemas/types.yaml#/definitions/phandle + description: | + The node of system control processor (SCP), using + the remoteproc & rpmsg framework. + + mediatek,venc-multi-core: + type: boolean + description: | + Indicates whether the encoder has multiple cores or not. + + iommus: + minItems: 1 + maxItems: 32 + description: | + List of the hardware port in respective IOMMU block for current Socs. + Refer to bindings/iommu/mediatek,iommu.yaml. + + dma-ranges: + maxItems: 1 + description: | + Describes the physical address space of IOMMU maps to memory. + + "#address-cells": + const: 2 + + "#size-cells": + const: 2 + + ranges: true + +# Required child node: +patternProperties: + "^venc-core@[0-9a-f]+$": + type: object + description: | + The video encoder core device node which should be added as subnodes to + the main venc node. + + properties: + compatible: + items: + - const: mediatek,mtk-venc-core + + reg: + maxItems: 1 + + mediatek,core-id: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Current encoder core id. + + iommus: + minItems: 1 + maxItems: 32 + description: | + List of the hardware port in respective IOMMU block for current Socs. + Refer to bindings/iommu/mediatek,iommu.yaml. + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + maxItems: 1 + + power-domains: + maxItems: 1 + + required: + - compatible + - reg + - mediatek,core-id + - iommus + - interrupts + - clocks + - clock-names + - assigned-clocks + - assigned-clock-parents + - power-domains + + additionalProperties: false + +required: + - compatible + - mediatek,scp + - iommus + - dma-ranges + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/memory/mt8195-memory-port.h> + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/clock/mt8195-clk.h> + #include <dt-bindings/power/mt8195-power.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + venc { + compatible = "mediatek,mt8195-vcodec-enc"; + mediatek,scp = <&scp>; + mediatek,venc-multi-core; + iommus = <&iommu_vdo M4U_PORT_L19_VENC_RCPU>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>; + + venc-core@1a020000 { + compatible = "mediatek,mtk-venc-core"; + reg = <0 0x1a020000 0 0x10000>; + mediatek,core-id = <0>; + iommus = <&iommu_vdo M4U_PORT_L19_VENC_RCPU>, + <&iommu_vdo M4U_PORT_L19_VENC_REC>, + <&iommu_vdo M4U_PORT_L19_VENC_BSDMA>, + <&iommu_vdo M4U_PORT_L19_VENC_SV_COMV>, + <&iommu_vdo M4U_PORT_L19_VENC_RD_COMV>, + <&iommu_vdo M4U_PORT_L19_VENC_CUR_LUMA>, + <&iommu_vdo M4U_PORT_L19_VENC_CUR_CHROMA>, + <&iommu_vdo M4U_PORT_L19_VENC_REF_LUMA>, + <&iommu_vdo M4U_PORT_L19_VENC_REF_CHROMA>; + interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&vencsys CLK_VENC_VENC>; + clock-names = "clk_venc"; + assigned-clocks = <&topckgen CLK_TOP_VENC>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>; + power-domains = <&spm MT8195_POWER_DOMAIN_VENC>; + }; + + venc-core@1b020000 { + compatible = "mediatek,mtk-venc-core"; + reg = <0 0x1b020000 0 0x10000>; + mediatek,core-id = <1>; + iommus = <&iommu_vpp M4U_PORT_L20_VENC_RCPU>, + <&iommu_vpp M4U_PORT_L20_VENC_REC>, + <&iommu_vpp M4U_PORT_L20_VENC_BSDMA>, + <&iommu_vpp M4U_PORT_L20_VENC_SV_COMV>, + <&iommu_vpp M4U_PORT_L20_VENC_RD_COMV>, + <&iommu_vpp M4U_PORT_L20_VENC_CUR_LUMA>, + <&iommu_vpp M4U_PORT_L20_VENC_CUR_CHROMA>, + <&iommu_vpp M4U_PORT_L20_VENC_REF_LUMA>, + <&iommu_vpp M4U_PORT_L20_VENC_REF_CHROMA>; + interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&vencsys_core1 CLK_VENC_CORE1_VENC>; + clock-names = "clk_venc_core1"; + assigned-clocks = <&topckgen CLK_TOP_VENC>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>; + power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/media/mediatek,vcodec-encoder.yaml b/Documentation/devicetree/bindings/media/mediatek,vcodec-encoder.yaml index e7b65a91c92c..0530a694bcbe 100644 --- a/Documentation/devicetree/bindings/media/mediatek,vcodec-encoder.yaml +++ b/Documentation/devicetree/bindings/media/mediatek,vcodec-encoder.yaml @@ -21,7 +21,6 @@ properties: - mediatek,mt8173-vcodec-enc - mediatek,mt8183-vcodec-enc - mediatek,mt8192-vcodec-enc - - mediatek,mt8195-vcodec-enc reg: maxItems: 1
Adds encoder cores dt-bindings for mt8195. Signed-off-by: Irui Wang <irui.wang@mediatek.com> --- .../media/mediatek,vcodec-encoder-core.yaml | 181 ++++++++++++++++++ .../media/mediatek,vcodec-encoder.yaml | 1 - 2 files changed, 181 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/media/mediatek,vcodec-encoder-core.yaml