diff mbox series

[08/14] EDAC/amd64: Add determine_edac_cap() into pvt->ops

Message ID 20220228161354.54923-9-nchatrad@amd.com (mailing list archive)
State New, archived
Headers show
Series EDAC/amd64: move platform specific routines to pvt->ops | expand

Commit Message

Naveen Krishna Chatradhi Feb. 28, 2022, 4:13 p.m. UTC 
From: Muralidhara M K <muralimk@amd.com>

Add function pointer for determine_edac_cap() in pvt->ops and assign
family specific determine_edac_cap() definitions appropriately.

Signed-off-by: Muralidhara M K <muralimk@amd.com>
Signed-off-by: Naveen Krishna Chatradhi <nchatrad@amd.com>
---
This patch is created by splitting the 5/12th patch in series
[v7 5/12] https://patchwork.kernel.org/project/linux-edac/patch/20220203174942.31630-6-nchatrad@amd.com/

 drivers/edac/amd64_edac.c | 37 ++++++++++++++++++++++++-------------
 drivers/edac/amd64_edac.h |  1 +
 2 files changed, 25 insertions(+), 13 deletions(-)

Comments

Yazen Ghannam March 28, 2022, 4:22 p.m. UTC | #1 
On Mon, Feb 28, 2022 at 09:43:48PM +0530, Naveen Krishna Chatradhi wrote:
> From: Muralidhara M K <muralimk@amd.com>
> 
> Add function pointer for determine_edac_cap() in pvt->ops and assign
> family specific determine_edac_cap() definitions appropriately.
>

Please include the "why".
 
> Signed-off-by: Muralidhara M K <muralimk@amd.com>
> Signed-off-by: Naveen Krishna Chatradhi <nchatrad@amd.com>
> ---
> This patch is created by splitting the 5/12th patch in series
> [v7 5/12] https://patchwork.kernel.org/project/linux-edac/patch/20220203174942.31630-6-nchatrad@amd.com/
> 
>  drivers/edac/amd64_edac.c | 37 ++++++++++++++++++++++++-------------
>  drivers/edac/amd64_edac.h |  1 +
>  2 files changed, 25 insertions(+), 13 deletions(-)
> 
> diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
> index 15d775a9ce7e..af6711cf03e9 100644
> --- a/drivers/edac/amd64_edac.c
> +++ b/drivers/edac/amd64_edac.c
> @@ -1267,13 +1267,25 @@ static int get_channel_from_ecc_syndrome(struct mem_ctl_info *, u16);
>   * Determine if the DIMMs have ECC enabled. ECC is enabled ONLY if all the DIMMs
>   * are ECC capable.
>   */
> -static unsigned long determine_edac_cap(struct amd64_pvt *pvt)
> +static unsigned long f1x_determine_edac_cap(struct amd64_pvt *pvt)
>  {
>  	unsigned long edac_cap = EDAC_FLAG_NONE;
>  	u8 bit;
>  
> -	if (pvt->umc) {
> -		u8 i, umc_en_mask = 0, dimm_ecc_en_mask = 0;
> +	bit = (pvt->fam > 0xf || pvt->ext_model >= K8_REV_F)
> +		? 19
> +		: 17;
> +
> +	if (pvt->dclr0 & BIT(bit))
> +		edac_cap = EDAC_FLAG_SECDED;
> +
> +	return edac_cap;
> +}
> +
> +static unsigned long f17_determine_edac_cap(struct amd64_pvt *pvt)
> +{
> +	u8 i, umc_en_mask = 0, dimm_ecc_en_mask = 0;
> +	unsigned long edac_cap = EDAC_FLAG_NONE;
>  
>  		for_each_umc(i) {
>  			if (!(pvt->umc[i].sdp_ctrl & UMC_SDP_INIT))
> @@ -1288,14 +1300,6 @@ static unsigned long determine_edac_cap(struct amd64_pvt *pvt)
>  
>  		if (umc_en_mask == dimm_ecc_en_mask)
>  			edac_cap = EDAC_FLAG_SECDED;
> -	} else {
> -		bit = (pvt->fam > 0xf || pvt->ext_model >= K8_REV_F)
> -			? 19
> -			: 17;
> -
> -		if (pvt->dclr0 & BIT(bit))
> -			edac_cap = EDAC_FLAG_SECDED;
> -	}
>  
>  	return edac_cap;
>  }
> @@ -3759,7 +3763,7 @@ static void setup_mci_misc_attrs(struct mem_ctl_info *mci)
>  			mci->edac_ctl_cap |= EDAC_FLAG_S4ECD4ED;

This patch is okay overall. But I think we should audit which EDAC_FLAG values
are used to make sure they truly match the system capabilities.

Thanks,
Yazen
diff mbox series

Patch

diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
index 15d775a9ce7e..af6711cf03e9 100644
--- a/drivers/edac/amd64_edac.c
+++ b/drivers/edac/amd64_edac.c
@@ -1267,13 +1267,25 @@  static int get_channel_from_ecc_syndrome(struct mem_ctl_info *, u16);
  * Determine if the DIMMs have ECC enabled. ECC is enabled ONLY if all the DIMMs
  * are ECC capable.
  */
-static unsigned long determine_edac_cap(struct amd64_pvt *pvt)
+static unsigned long f1x_determine_edac_cap(struct amd64_pvt *pvt)
 {
 	unsigned long edac_cap = EDAC_FLAG_NONE;
 	u8 bit;
 
-	if (pvt->umc) {
-		u8 i, umc_en_mask = 0, dimm_ecc_en_mask = 0;
+	bit = (pvt->fam > 0xf || pvt->ext_model >= K8_REV_F)
+		? 19
+		: 17;
+
+	if (pvt->dclr0 & BIT(bit))
+		edac_cap = EDAC_FLAG_SECDED;
+
+	return edac_cap;
+}
+
+static unsigned long f17_determine_edac_cap(struct amd64_pvt *pvt)
+{
+	u8 i, umc_en_mask = 0, dimm_ecc_en_mask = 0;
+	unsigned long edac_cap = EDAC_FLAG_NONE;
 
 		for_each_umc(i) {
 			if (!(pvt->umc[i].sdp_ctrl & UMC_SDP_INIT))
@@ -1288,14 +1300,6 @@  static unsigned long determine_edac_cap(struct amd64_pvt *pvt)
 
 		if (umc_en_mask == dimm_ecc_en_mask)
 			edac_cap = EDAC_FLAG_SECDED;
-	} else {
-		bit = (pvt->fam > 0xf || pvt->ext_model >= K8_REV_F)
-			? 19
-			: 17;
-
-		if (pvt->dclr0 & BIT(bit))
-			edac_cap = EDAC_FLAG_SECDED;
-	}
 
 	return edac_cap;
 }
@@ -3759,7 +3763,7 @@  static void setup_mci_misc_attrs(struct mem_ctl_info *mci)
 			mci->edac_ctl_cap |= EDAC_FLAG_S4ECD4ED;
 	}
 
-	mci->edac_cap		= determine_edac_cap(pvt);
+	mci->edac_cap		= pvt->ops->determine_edac_cap(pvt);
 	mci->mod_name		= EDAC_MOD_STR;
 	mci->ctl_name		= pvt->ctl_name;
 	mci->dev_name		= pci_name(pvt->F3);
@@ -3796,6 +3800,7 @@  static int per_family_init(struct amd64_pvt *pvt)
 		pvt->ops->determine_ecc_sym_sz		= f1x_determine_ecc_sym_sz;
 		pvt->ops->get_mc_regs			= read_mc_regs;
 		pvt->ops->ecc_enabled			= f1x_ecc_enabled;
+		pvt->ops->determine_edac_cap		= f1x_determine_edac_cap;
 		break;
 
 	case 0x10:
@@ -3811,6 +3816,7 @@  static int per_family_init(struct amd64_pvt *pvt)
 		pvt->ops->determine_ecc_sym_sz		= f1x_determine_ecc_sym_sz;
 		pvt->ops->get_mc_regs			= read_mc_regs;
 		pvt->ops->ecc_enabled			= f1x_ecc_enabled;
+		pvt->ops->determine_edac_cap		= f1x_determine_edac_cap;
 		break;
 
 	case 0x15:
@@ -3842,6 +3848,7 @@  static int per_family_init(struct amd64_pvt *pvt)
 		pvt->ops->determine_ecc_sym_sz		= f1x_determine_ecc_sym_sz;
 		pvt->ops->get_mc_regs			= read_mc_regs;
 		pvt->ops->ecc_enabled			= f1x_ecc_enabled;
+		pvt->ops->determine_edac_cap		= f1x_determine_edac_cap;
 		break;
 
 	case 0x16:
@@ -3863,6 +3870,7 @@  static int per_family_init(struct amd64_pvt *pvt)
 		pvt->ops->determine_ecc_sym_sz		= f1x_determine_ecc_sym_sz;
 		pvt->ops->get_mc_regs			= read_mc_regs;
 		pvt->ops->ecc_enabled			= f1x_ecc_enabled;
+		pvt->ops->determine_edac_cap		= f1x_determine_edac_cap;
 		break;
 
 	case 0x17:
@@ -3898,6 +3906,7 @@  static int per_family_init(struct amd64_pvt *pvt)
 		pvt->ops->determine_ecc_sym_sz		= f17_determine_ecc_sym_sz;
 		pvt->ops->get_mc_regs			= __read_mc_regs_df;
 		pvt->ops->ecc_enabled			= f17_ecc_enabled;
+		pvt->ops->determine_edac_cap		= f17_determine_edac_cap;
 
 		if (pvt->fam == 0x18) {
 			pvt->ctl_name			= "F18h";
@@ -3939,6 +3948,7 @@  static int per_family_init(struct amd64_pvt *pvt)
 		pvt->ops->determine_ecc_sym_sz		= f17_determine_ecc_sym_sz;
 		pvt->ops->get_mc_regs			= __read_mc_regs_df;
 		pvt->ops->ecc_enabled			= f17_ecc_enabled;
+		pvt->ops->determine_edac_cap		= f17_determine_edac_cap;
 		break;
 
 	default:
@@ -3950,7 +3960,8 @@  static int per_family_init(struct amd64_pvt *pvt)
 	if (!pvt->ops->early_channel_count || !pvt->ops->dbam_to_cs ||
 	    !pvt->ops->get_base_mask || !pvt->ops->prep_chip_selects ||
 	    !pvt->ops->determine_memory_type || !pvt->ops->determine_ecc_sym_sz ||
-	    !pvt->ops->get_mc_regs || !pvt->ops->ecc_enabled) {
+	    !pvt->ops->get_mc_regs || !pvt->ops->ecc_enabled ||
+	    !pvt->ops->determine_edac_cap) {
 		edac_dbg(1, "Common helper routines not defined.\n");
 		return -EFAULT;
 	}
diff --git a/drivers/edac/amd64_edac.h b/drivers/edac/amd64_edac.h
index 6cc3fc943fcd..9a789cb01f4d 100644
--- a/drivers/edac/amd64_edac.h
+++ b/drivers/edac/amd64_edac.h
@@ -470,6 +470,7 @@  struct low_ops {
 	void (*determine_ecc_sym_sz)(struct amd64_pvt *pvt);
 	void (*get_mc_regs)(struct amd64_pvt *pvt);
 	bool (*ecc_enabled)(struct amd64_pvt *pvt);
+	unsigned long (*determine_edac_cap)(struct amd64_pvt *pvt);
 };
 
 int __amd64_read_pci_cfg_dword(struct pci_dev *pdev, int offset,