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[12/14] EDAC/amd64: Add dump_misc_regs() into pvt->ops

Message ID 20220228161354.54923-13-nchatrad@amd.com (mailing list archive)
State New, archived
Headers show
Series EDAC/amd64: move platform specific routines to pvt->ops | expand

Commit Message

Naveen Krishna Chatradhi Feb. 28, 2022, 4:13 p.m. UTC 
From: Muralidhara M K <muralimk@amd.com>

Add function pointer for dump_misc_regs() in pvt->ops and assign
family specific dump_misc_regs() definitions appropriately.

Signed-off-by: Muralidhara M K <muralimk@amd.com>
Signed-off-by: Naveen Krishna Chatradhi <nchatrad@amd.com>
---
This patch is created by splitting the 5/12th patch in series
[v7 5/12] https://patchwork.kernel.org/project/linux-edac/patch/20220203174942.31630-6-nchatrad@amd.com/

 drivers/edac/amd64_edac.c | 25 ++++++++++++++-----------
 drivers/edac/amd64_edac.h |  1 +
 2 files changed, 15 insertions(+), 11 deletions(-)

Comments

Yazen Ghannam March 28, 2022, 4:58 p.m. UTC | #1 
On Mon, Feb 28, 2022 at 09:43:52PM +0530, Naveen Krishna Chatradhi wrote:
> From: Muralidhara M K <muralimk@amd.com>
> 
> Add function pointer for dump_misc_regs() in pvt->ops and assign
> family specific dump_misc_regs() definitions appropriately.

Please include the "why".

> 
> Signed-off-by: Muralidhara M K <muralimk@amd.com>
> Signed-off-by: Naveen Krishna Chatradhi <nchatrad@amd.com>
> ---
> This patch is created by splitting the 5/12th patch in series
> [v7 5/12] https://patchwork.kernel.org/project/linux-edac/patch/20220203174942.31630-6-nchatrad@amd.com/
> 
>  drivers/edac/amd64_edac.c | 25 ++++++++++++++-----------
>  drivers/edac/amd64_edac.h |  1 +
>  2 files changed, 15 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
> index a799594c9574..1063dda20ce9 100644
> --- a/drivers/edac/amd64_edac.c
> +++ b/drivers/edac/amd64_edac.c
> @@ -1442,6 +1442,10 @@ static void __dump_misc_regs_df(struct amd64_pvt *pvt)
>  
>  	edac_dbg(1, "F0x104 (DRAM Hole Address): 0x%08x, base: 0x%08x\n",
>  		 pvt->dhar, dhar_base(pvt));
> +
> +	edac_dbg(1, "  DramHoleValid: %s\n", dhar_valid(pvt) ? "yes" : "no");
> +

This line can be dropped when dhar is removed for current systems.

> +	amd64_info("using x%u syndromes.\n", pvt->ecc_sym_sz);

This line can be dropped if we decide that symbol size isn't needed on current
systems. We should double check if it's needed when determining "edac_mode".

If we keep it, then it should be printed at the end of the function where we
read the symbol size.

>  }
>  
>  /* Display and decode various NB registers for debug purposes. */
> @@ -1476,15 +1480,6 @@ static void __dump_misc_regs(struct amd64_pvt *pvt)
>  	/* Only if NOT ganged does dclr1 have valid info */
>  	if (!dct_ganging_enabled(pvt))
>  		debug_dump_dramcfg_low(pvt, pvt->dclr1, 1);
> -}
> -
> -/* Display and decode various NB registers for debug purposes. */
> -static void dump_misc_regs(struct amd64_pvt *pvt)
> -{
> -	if (pvt->umc)
> -		__dump_misc_regs_df(pvt);
> -	else
> -		__dump_misc_regs(pvt);
>  
>  	edac_dbg(1, "  DramHoleValid: %s\n", dhar_valid(pvt) ? "yes" : "no");
>  
> @@ -3803,6 +3798,7 @@ static int per_family_init(struct amd64_pvt *pvt)
>  		pvt->ops->determine_edac_ctl_cap	= f1x_determine_edac_ctl_cap;
>  		pvt->ops->setup_mci_misc_attrs		= f1x_setup_mci_misc_attrs;
>  		pvt->ops->populate_csrows		= init_csrows;
> +		pvt->ops->dump_misc_regs		= __dump_misc_regs;
>  		break;
>  
>  	case 0x10:
> @@ -3822,6 +3818,7 @@ static int per_family_init(struct amd64_pvt *pvt)
>  		pvt->ops->determine_edac_ctl_cap	= f1x_determine_edac_ctl_cap;
>  		pvt->ops->setup_mci_misc_attrs		= f1x_setup_mci_misc_attrs;
>  		pvt->ops->populate_csrows		= init_csrows;
> +		pvt->ops->dump_misc_regs		= __dump_misc_regs;
>  		break;
>  
>  	case 0x15:
> @@ -3857,6 +3854,7 @@ static int per_family_init(struct amd64_pvt *pvt)
>  		pvt->ops->determine_edac_ctl_cap	= f1x_determine_edac_ctl_cap;
>  		pvt->ops->setup_mci_misc_attrs		= f1x_setup_mci_misc_attrs;
>  		pvt->ops->populate_csrows		= init_csrows;
> +		pvt->ops->dump_misc_regs		= __dump_misc_regs;
>  		break;
>  
>  	case 0x16:
> @@ -3882,6 +3880,7 @@ static int per_family_init(struct amd64_pvt *pvt)
>  		pvt->ops->determine_edac_ctl_cap	= f1x_determine_edac_ctl_cap;
>  		pvt->ops->setup_mci_misc_attrs		= f1x_setup_mci_misc_attrs;
>  		pvt->ops->populate_csrows		= init_csrows;
> +		pvt->ops->dump_misc_regs		= __dump_misc_regs;
>  		break;
>  
>  	case 0x17:
> @@ -3921,6 +3920,7 @@ static int per_family_init(struct amd64_pvt *pvt)
>  		pvt->ops->determine_edac_ctl_cap	= f17_determine_edac_ctl_cap;
>  		pvt->ops->setup_mci_misc_attrs		= f1x_setup_mci_misc_attrs;
>  		pvt->ops->populate_csrows		= init_csrows_df;
> +		pvt->ops->dump_misc_regs		= __dump_misc_regs_df;
>  
>  		if (pvt->fam == 0x18) {
>  			pvt->ctl_name			= "F18h";
> @@ -3966,6 +3966,7 @@ static int per_family_init(struct amd64_pvt *pvt)
>  		pvt->ops->determine_edac_ctl_cap	= f17_determine_edac_ctl_cap;
>  		pvt->ops->setup_mci_misc_attrs		= f1x_setup_mci_misc_attrs;
>  		pvt->ops->populate_csrows		= init_csrows_df;
> +		pvt->ops->dump_misc_regs		= __dump_misc_regs_df;

I think the underscore prefixes can be dropped.

>  		break;
>  
>  	default:
> @@ -3979,7 +3980,8 @@ static int per_family_init(struct amd64_pvt *pvt)
>  	    !pvt->ops->determine_memory_type || !pvt->ops->determine_ecc_sym_sz ||
>  	    !pvt->ops->get_mc_regs || !pvt->ops->ecc_enabled ||
>  	    !pvt->ops->determine_edac_cap || !pvt->ops->determine_edac_ctl_cap ||
> -	    !pvt->ops->setup_mci_misc_attrs || !pvt->ops->populate_csrows) {
> +	    !pvt->ops->setup_mci_misc_attrs || !pvt->ops->populate_csrows ||
> +	    !pvt->ops->dump_misc_regs) {
>  		edac_dbg(1, "Common helper routines not defined.\n");
>  		return -EFAULT;
>  	}
> @@ -4169,7 +4171,8 @@ static int probe_one_instance(unsigned int nid)
>  
>  	amd64_info("%s detected (node %d).\n", pvt->ctl_name, pvt->mc_node_id);
>  
> -	dump_misc_regs(pvt);
> +	/* Display and decode various NB registers for debug purposes. */

Please drop "NB" from the comment since other registers can also be printed.

Thanks,
Yazen
diff mbox series

Patch

diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
index a799594c9574..1063dda20ce9 100644
--- a/drivers/edac/amd64_edac.c
+++ b/drivers/edac/amd64_edac.c
@@ -1442,6 +1442,10 @@  static void __dump_misc_regs_df(struct amd64_pvt *pvt)
 
 	edac_dbg(1, "F0x104 (DRAM Hole Address): 0x%08x, base: 0x%08x\n",
 		 pvt->dhar, dhar_base(pvt));
+
+	edac_dbg(1, "  DramHoleValid: %s\n", dhar_valid(pvt) ? "yes" : "no");
+
+	amd64_info("using x%u syndromes.\n", pvt->ecc_sym_sz);
 }
 
 /* Display and decode various NB registers for debug purposes. */
@@ -1476,15 +1480,6 @@  static void __dump_misc_regs(struct amd64_pvt *pvt)
 	/* Only if NOT ganged does dclr1 have valid info */
 	if (!dct_ganging_enabled(pvt))
 		debug_dump_dramcfg_low(pvt, pvt->dclr1, 1);
-}
-
-/* Display and decode various NB registers for debug purposes. */
-static void dump_misc_regs(struct amd64_pvt *pvt)
-{
-	if (pvt->umc)
-		__dump_misc_regs_df(pvt);
-	else
-		__dump_misc_regs(pvt);
 
 	edac_dbg(1, "  DramHoleValid: %s\n", dhar_valid(pvt) ? "yes" : "no");
 
@@ -3803,6 +3798,7 @@  static int per_family_init(struct amd64_pvt *pvt)
 		pvt->ops->determine_edac_ctl_cap	= f1x_determine_edac_ctl_cap;
 		pvt->ops->setup_mci_misc_attrs		= f1x_setup_mci_misc_attrs;
 		pvt->ops->populate_csrows		= init_csrows;
+		pvt->ops->dump_misc_regs		= __dump_misc_regs;
 		break;
 
 	case 0x10:
@@ -3822,6 +3818,7 @@  static int per_family_init(struct amd64_pvt *pvt)
 		pvt->ops->determine_edac_ctl_cap	= f1x_determine_edac_ctl_cap;
 		pvt->ops->setup_mci_misc_attrs		= f1x_setup_mci_misc_attrs;
 		pvt->ops->populate_csrows		= init_csrows;
+		pvt->ops->dump_misc_regs		= __dump_misc_regs;
 		break;
 
 	case 0x15:
@@ -3857,6 +3854,7 @@  static int per_family_init(struct amd64_pvt *pvt)
 		pvt->ops->determine_edac_ctl_cap	= f1x_determine_edac_ctl_cap;
 		pvt->ops->setup_mci_misc_attrs		= f1x_setup_mci_misc_attrs;
 		pvt->ops->populate_csrows		= init_csrows;
+		pvt->ops->dump_misc_regs		= __dump_misc_regs;
 		break;
 
 	case 0x16:
@@ -3882,6 +3880,7 @@  static int per_family_init(struct amd64_pvt *pvt)
 		pvt->ops->determine_edac_ctl_cap	= f1x_determine_edac_ctl_cap;
 		pvt->ops->setup_mci_misc_attrs		= f1x_setup_mci_misc_attrs;
 		pvt->ops->populate_csrows		= init_csrows;
+		pvt->ops->dump_misc_regs		= __dump_misc_regs;
 		break;
 
 	case 0x17:
@@ -3921,6 +3920,7 @@  static int per_family_init(struct amd64_pvt *pvt)
 		pvt->ops->determine_edac_ctl_cap	= f17_determine_edac_ctl_cap;
 		pvt->ops->setup_mci_misc_attrs		= f1x_setup_mci_misc_attrs;
 		pvt->ops->populate_csrows		= init_csrows_df;
+		pvt->ops->dump_misc_regs		= __dump_misc_regs_df;
 
 		if (pvt->fam == 0x18) {
 			pvt->ctl_name			= "F18h";
@@ -3966,6 +3966,7 @@  static int per_family_init(struct amd64_pvt *pvt)
 		pvt->ops->determine_edac_ctl_cap	= f17_determine_edac_ctl_cap;
 		pvt->ops->setup_mci_misc_attrs		= f1x_setup_mci_misc_attrs;
 		pvt->ops->populate_csrows		= init_csrows_df;
+		pvt->ops->dump_misc_regs		= __dump_misc_regs_df;
 		break;
 
 	default:
@@ -3979,7 +3980,8 @@  static int per_family_init(struct amd64_pvt *pvt)
 	    !pvt->ops->determine_memory_type || !pvt->ops->determine_ecc_sym_sz ||
 	    !pvt->ops->get_mc_regs || !pvt->ops->ecc_enabled ||
 	    !pvt->ops->determine_edac_cap || !pvt->ops->determine_edac_ctl_cap ||
-	    !pvt->ops->setup_mci_misc_attrs || !pvt->ops->populate_csrows) {
+	    !pvt->ops->setup_mci_misc_attrs || !pvt->ops->populate_csrows ||
+	    !pvt->ops->dump_misc_regs) {
 		edac_dbg(1, "Common helper routines not defined.\n");
 		return -EFAULT;
 	}
@@ -4169,7 +4171,8 @@  static int probe_one_instance(unsigned int nid)
 
 	amd64_info("%s detected (node %d).\n", pvt->ctl_name, pvt->mc_node_id);
 
-	dump_misc_regs(pvt);
+	/* Display and decode various NB registers for debug purposes. */
+	pvt->ops->dump_misc_regs(pvt);
 
 	return ret;
 
diff --git a/drivers/edac/amd64_edac.h b/drivers/edac/amd64_edac.h
index c762b341650f..7b377dba0dc7 100644
--- a/drivers/edac/amd64_edac.h
+++ b/drivers/edac/amd64_edac.h
@@ -474,6 +474,7 @@  struct low_ops {
 	void (*determine_edac_ctl_cap)(struct mem_ctl_info *mci, struct amd64_pvt *pvt);
 	void (*setup_mci_misc_attrs)(struct mem_ctl_info *mci);
 	int  (*populate_csrows)(struct mem_ctl_info *mci);
+	void (*dump_misc_regs)(struct amd64_pvt *pvt);
 };
 
 int __amd64_read_pci_cfg_dword(struct pci_dev *pdev, int offset,