diff mbox series

[v4,3/4] arm64: dts: imx8mp: Add MEDIAMIX power domains

Message ID 20220328072009.1441-4-laurent.pinchart@ideasonboard.com (mailing list archive)
State New, archived
Headers show
Series imx8mp: Add media block control | expand

Commit Message

Laurent Pinchart March 28, 2022, 7:20 a.m. UTC 
Add the power domains related to the MEDIAMIX to the GPC.

Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Marek Vasut <marex@denx.de>
---
Changes since v2:

- Drop assigned clocks, they moved to the media-blk-ctrl node
---
 arch/arm64/boot/dts/freescale/imx8mp.dtsi | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

Comments

Paul Elder March 30, 2022, 9:56 a.m. UTC | #1 
Hi Laurent,

On Mon, Mar 28, 2022 at 10:20:08AM +0300, Laurent Pinchart wrote:
> Add the power domains related to the MEDIAMIX to the GPC.
> 
> Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> Reviewed-by: Marek Vasut <marex@denx.de>

Reviewed-by: Paul Elder <paul.elder@ideasonboard.com>

> ---
> Changes since v2:
> 
> - Drop assigned clocks, they moved to the media-blk-ctrl node
> ---
>  arch/arm64/boot/dts/freescale/imx8mp.dtsi | 23 +++++++++++++++++++++++
>  1 file changed, 23 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> index 096139d7c365..55f2fa2a562d 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> @@ -488,6 +488,11 @@ pgc {
>  					#address-cells = <1>;
>  					#size-cells = <0>;
>  
> +					pgc_mipi_phy1: power-domain@0 {
> +						#power-domain-cells = <0>;
> +						reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY1>;
> +					};
> +
>  					pgc_pcie_phy: power-domain@1 {
>  						#power-domain-cells = <0>;
>  						reg = <IMX8MP_POWER_DOMAIN_PCIE_PHY>;
> @@ -530,6 +535,18 @@ pgc_gpu3d: power-domain@9 {
>  						power-domains = <&pgc_gpumix>;
>  					};
>  
> +					pgc_mediamix: power-domain@10 {
> +						#power-domain-cells = <0>;
> +						reg = <IMX8MP_POWER_DOMAIN_MEDIAMIX>;
> +						clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
> +							 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
> +					};
> +
> +					pgc_mipi_phy2: power-domain@16 {
> +						#power-domain-cells = <0>;
> +						reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY2>;
> +					};
> +
>  					pgc_hsiomix: power-domains@17 {
>  						#power-domain-cells = <0>;
>  						reg = <IMX8MP_POWER_DOMAIN_HSIOMIX>;
> @@ -539,6 +556,12 @@ pgc_hsiomix: power-domains@17 {
>  						assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
>  						assigned-clock-rates = <500000000>;
>  					};
> +
> +					pgc_ispdwp: power-domain@18 {
> +						#power-domain-cells = <0>;
> +						reg = <IMX8MP_POWER_DOMAIN_MEDIAMIX_ISPDWP>;
> +						clocks = <&clk IMX8MP_CLK_MEDIA_ISP_DIV>;
> +					};
>  				};
>  			};
>  		};
> -- 
> Regards,
> 
> Laurent Pinchart
>
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index 096139d7c365..55f2fa2a562d 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -488,6 +488,11 @@  pgc {
 					#address-cells = <1>;
 					#size-cells = <0>;
 
+					pgc_mipi_phy1: power-domain@0 {
+						#power-domain-cells = <0>;
+						reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY1>;
+					};
+
 					pgc_pcie_phy: power-domain@1 {
 						#power-domain-cells = <0>;
 						reg = <IMX8MP_POWER_DOMAIN_PCIE_PHY>;
@@ -530,6 +535,18 @@  pgc_gpu3d: power-domain@9 {
 						power-domains = <&pgc_gpumix>;
 					};
 
+					pgc_mediamix: power-domain@10 {
+						#power-domain-cells = <0>;
+						reg = <IMX8MP_POWER_DOMAIN_MEDIAMIX>;
+						clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
+							 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
+					};
+
+					pgc_mipi_phy2: power-domain@16 {
+						#power-domain-cells = <0>;
+						reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY2>;
+					};
+
 					pgc_hsiomix: power-domains@17 {
 						#power-domain-cells = <0>;
 						reg = <IMX8MP_POWER_DOMAIN_HSIOMIX>;
@@ -539,6 +556,12 @@  pgc_hsiomix: power-domains@17 {
 						assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
 						assigned-clock-rates = <500000000>;
 					};
+
+					pgc_ispdwp: power-domain@18 {
+						#power-domain-cells = <0>;
+						reg = <IMX8MP_POWER_DOMAIN_MEDIAMIX_ISPDWP>;
+						clocks = <&clk IMX8MP_CLK_MEDIA_ISP_DIV>;
+					};
 				};
 			};
 		};