| Message ID | 20220404100508.3209-1-wsa+renesas@sang-engineering.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v2] mmc: renesas_sdhi: special 4tap settings only apply to HS400 | expand |
On Mon, 4 Apr 2022 at 12:05, Wolfram Sang <wsa+renesas@sang-engineering.com> wrote: > > Previous documentation was vague, so we included SDR104 for slow SDnH > clock settings. It turns out now, that it is only needed for HS400. > > Fixes: bb6d3fa98a41 ("clk: renesas: rcar-gen3: Switch to new SD clock handling") > Reported-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> > Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> > Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Applied for fixes, thanks! Kind regards Uffe > --- > > Chages since v1: > * fixed typo in the commit message (Shimoda-san) > * added review tag > > drivers/mmc/host/renesas_sdhi_core.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/mmc/host/renesas_sdhi_core.c b/drivers/mmc/host/renesas_sdhi_core.c > index fe63548d816d..89d21231ec5f 100644 > --- a/drivers/mmc/host/renesas_sdhi_core.c > +++ b/drivers/mmc/host/renesas_sdhi_core.c > @@ -142,9 +142,9 @@ static unsigned int renesas_sdhi_clk_update(struct tmio_mmc_host *host, > return clk_get_rate(priv->clk); > > if (priv->clkh) { > + /* HS400 with 4TAP needs different clock settings */ > bool use_4tap = priv->quirks && priv->quirks->hs400_4taps; > - bool need_slow_clkh = (host->mmc->ios.timing == MMC_TIMING_UHS_SDR104) || > - (host->mmc->ios.timing == MMC_TIMING_MMC_HS400); > + bool need_slow_clkh = host->mmc->ios.timing == MMC_TIMING_MMC_HS400; > clkh_shift = use_4tap && need_slow_clkh ? 1 : 2; > ref_clk = priv->clkh; > } > -- > 2.30.2 >
On Tue, Apr 5, 2022 at 2:26 AM Wolfram Sang <wsa+renesas@sang-engineering.com> wrote: > Previous documentation was vague, so we included SDR104 for slow SDnH > clock settings. It turns out now, that it is only needed for HS400. > > Fixes: bb6d3fa98a41 ("clk: renesas: rcar-gen3: Switch to new SD clock handling") > Reported-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> > Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> > Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
diff --git a/drivers/mmc/host/renesas_sdhi_core.c b/drivers/mmc/host/renesas_sdhi_core.c index fe63548d816d..89d21231ec5f 100644 --- a/drivers/mmc/host/renesas_sdhi_core.c +++ b/drivers/mmc/host/renesas_sdhi_core.c @@ -142,9 +142,9 @@ static unsigned int renesas_sdhi_clk_update(struct tmio_mmc_host *host, return clk_get_rate(priv->clk); if (priv->clkh) { + /* HS400 with 4TAP needs different clock settings */ bool use_4tap = priv->quirks && priv->quirks->hs400_4taps; - bool need_slow_clkh = (host->mmc->ios.timing == MMC_TIMING_UHS_SDR104) || - (host->mmc->ios.timing == MMC_TIMING_MMC_HS400); + bool need_slow_clkh = host->mmc->ios.timing == MMC_TIMING_MMC_HS400; clkh_shift = use_4tap && need_slow_clkh ? 1 : 2; ref_clk = priv->clkh; }
Previous documentation was vague, so we included SDR104 for slow SDnH clock settings. It turns out now, that it is only needed for HS400. Fixes: bb6d3fa98a41 ("clk: renesas: rcar-gen3: Switch to new SD clock handling") Reported-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> --- Chages since v1: * fixed typo in the commit message (Shimoda-san) * added review tag drivers/mmc/host/renesas_sdhi_core.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)