| Message ID | 20220404173453.2632031-1-lucas.demarchi@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [CI] drm/i915/uncore: keep track of last mmio accesses | expand |
On Mon, Apr 04, 2022 at 10:34:53AM -0700, Lucas De Marchi wrote: >Sine gen6 we use FPGA_DBG register to detect unclaimed MMIO registers. >This register is in the display engine IP and can only ever detect >unclaimed accesses to registers in this area. However sometimes there >are reports of this triggering for registers in other areas, which >should not be possible. > >This keeps track of the last 4 registers which should hopefully be >sufficient to understand where these are coming from. And without >increasing the debug struct too much: > >Before: > struct intel_uncore_mmio_debug { > spinlock_t lock; /* 0 64 */ > /* --- cacheline 1 boundary (64 bytes) --- */ > int unclaimed_mmio_check; /* 64 4 */ > int saved_mmio_check; /* 68 4 */ > u32 suspend_count; /* 72 4 */ > > /* size: 80, cachelines: 2, members: 4 */ > /* padding: 4 */ > /* last cacheline: 16 bytes */ > }; > >After: > struct intel_uncore_mmio_debug { > spinlock_t lock; /* 0 64 */ > /* --- cacheline 1 boundary (64 bytes) --- */ > int unclaimed_mmio_check; /* 64 4 */ > int saved_mmio_check; /* 68 4 */ > u32 last_reg[4]; /* 72 16 */ > u32 last_reg_pos; /* 88 4 */ > u32 suspend_count; /* 92 4 */ > > /* size: 96, cachelines: 2, members: 6 */ > /* last cacheline: 32 bytes */ > }; > >Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> >--- > >Sending this for CI only for now, to get it running and hopefully >reproduce the issues we are seeing. I didn't reproduce the issue >mentioned with this patch applied yet. nvm, found a way to reproduce it locally and fix up the output reporting. I canceled the CI execution and will submit it again. Lucas De Marchi
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c index 8b9caaaacc21..4cb6372026a4 100644 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@ -1509,9 +1509,24 @@ __unclaimed_reg_debug(struct intel_uncore *uncore, check_for_unclaimed_mmio(uncore) && !before, "Unclaimed %s register 0x%x\n", read ? "read from" : "write to", - i915_mmio_reg_offset(reg))) + i915_mmio_reg_offset(reg))) { + unsigned int i = 0; + /* Only report the first N failures */ uncore->i915->params.mmio_debug--; + + drm_dbg(&uncore->i915->drm, "Last register accesses:\n"); + while (i < INTEL_UNCORE_MMIO_DEBUG_REG_COUNT) { + drm_dbg(&uncore->i915->drm, "0x%x\n", + uncore->debug->last_reg[(uncore->debug->last_reg_pos + i) % INTEL_UNCORE_MMIO_DEBUG_REG_COUNT]); + } + } + + if (!before) { + uncore->debug->last_reg[uncore->debug->last_reg_pos++] = + i915_mmio_reg_offset(reg); + uncore->debug->last_reg_pos %= INTEL_UNCORE_MMIO_DEBUG_REG_COUNT; + } } static inline void diff --git a/drivers/gpu/drm/i915/intel_uncore.h b/drivers/gpu/drm/i915/intel_uncore.h index 52fe3d89dd2b..5b5d2858ae11 100644 --- a/drivers/gpu/drm/i915/intel_uncore.h +++ b/drivers/gpu/drm/i915/intel_uncore.h @@ -38,10 +38,14 @@ struct intel_runtime_pm; struct intel_uncore; struct intel_gt; +#define INTEL_UNCORE_MMIO_DEBUG_REG_COUNT 4 + struct intel_uncore_mmio_debug { spinlock_t lock; /** lock is also taken in irq contexts. */ int unclaimed_mmio_check; int saved_mmio_check; + u32 last_reg[INTEL_UNCORE_MMIO_DEBUG_REG_COUNT]; + u32 last_reg_pos; u32 suspend_count; };
Sine gen6 we use FPGA_DBG register to detect unclaimed MMIO registers. This register is in the display engine IP and can only ever detect unclaimed accesses to registers in this area. However sometimes there are reports of this triggering for registers in other areas, which should not be possible. This keeps track of the last 4 registers which should hopefully be sufficient to understand where these are coming from. And without increasing the debug struct too much: Before: struct intel_uncore_mmio_debug { spinlock_t lock; /* 0 64 */ /* --- cacheline 1 boundary (64 bytes) --- */ int unclaimed_mmio_check; /* 64 4 */ int saved_mmio_check; /* 68 4 */ u32 suspend_count; /* 72 4 */ /* size: 80, cachelines: 2, members: 4 */ /* padding: 4 */ /* last cacheline: 16 bytes */ }; After: struct intel_uncore_mmio_debug { spinlock_t lock; /* 0 64 */ /* --- cacheline 1 boundary (64 bytes) --- */ int unclaimed_mmio_check; /* 64 4 */ int saved_mmio_check; /* 68 4 */ u32 last_reg[4]; /* 72 16 */ u32 last_reg_pos; /* 88 4 */ u32 suspend_count; /* 92 4 */ /* size: 96, cachelines: 2, members: 6 */ /* last cacheline: 32 bytes */ }; Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> --- Sending this for CI only for now, to get it running and hopefully reproduce the issues we are seeing. I didn't reproduce the issue mentioned with this patch applied yet. drivers/gpu/drm/i915/intel_uncore.c | 17 ++++++++++++++++- drivers/gpu/drm/i915/intel_uncore.h | 4 ++++ 2 files changed, 20 insertions(+), 1 deletion(-)