| Message ID | 20220404123553.25851-1-prabhakar.mahadev-lad.rj@bp.renesas.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | Add RSPI/OSTM/WDT/TSU/OPP support to Renesas RZ/G2L SoC | expand |
Hi! > This patch series adds support for following to Renesas RZ/RGL SoC: > * RSPI > * WDT > * OSTM > * TSU/OPP/IPA > > All the patches have been cherry-picked from v5.17 release. Thanks for the series. It passes testing and I do not see any problems that would prevent merge. I can merge it if there are no other comments. Best regards, Pavel
Hi all, > > Hi All, > > This patch series adds support for following to Renesas RZ/RGL SoC: > * RSPI > * WDT > * OSTM > * TSU/OPP/IPA > > All the patches have been cherry-picked from v5.17 release. Looks good to me this series. I applied to Linux-5.10.y-cip tree. Best regards, Nobuhiro
Hi Nobuhiro, Pavel, > -----Original Message----- > From: nobuhiro1.iwamatsu@toshiba.co.jp <nobuhiro1.iwamatsu@toshiba.co.jp> > Sent: 05 April 2022 08:46 > To: Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>; cip- > dev@lists.cip-project.org; pavel@denx.de > Cc: Biju Das <biju.das.jz@bp.renesas.com> > Subject: RE: [PATCH 5.10.y-cip 00/29] Add RSPI/OSTM/WDT/TSU/OPP support to > Renesas RZ/G2L SoC > > Hi all, > > > > > Hi All, > > > > This patch series adds support for following to Renesas RZ/RGL SoC: > > * RSPI > > * WDT > > * OSTM > > * TSU/OPP/IPA > > > > All the patches have been cherry-picked from v5.17 release. > > Looks good to me this series. > I applied to Linux-5.10.y-cip tree. > Thank you for the review and acceptance. Cheers, Prabhakar
Hi! > From: Biju Das <biju.das.jz@bp.renesas.com> > > commit 673c68bd48390dad01f7d17670de3e33b60860ac upstream. > > The RZ/G2L SoC incorporates a thermal sensor unit (TSU) that measures the > temperature inside the LSI. > > The thermal sensor in this unit measures temperatures in the range from > −40 degree Celsius to 125 degree Celsius with an accuracy of ±3°C. The > TSU repeats measurement at 20 microseconds intervals and automatically > updates the results of measurement. > > The TSU has no interrupts as well as no external pins. > > This patch adds Thermal Sensor Unit(TSU) driver for RZ/G2L SoC. > + /* TSU repeats measurement at 20 microseconds intervals and ... > + * ts_code_ave = (ts_code[0] + ⋯ + ts_code[7]) / 8 > + */ > + /* The temperature Tj is calculated by the formula > + * Tj = (dsensor − calib1) * 165/ (calib0 − calib1) − 40 > + * where calib0 and calib1 are the caliberation values. > + */ I'd avoid using non-ASCII characters where possible. ... is not that much longer, and that symbol should really be -. Also comments should start with /* on separate line, but that's really detail. Best regards, Pavel
Hi Pavel, Thank you for the review. > -----Original Message----- > From: Pavel Machek <pavel@denx.de> > Sent: 05 April 2022 20:06 > To: Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com> > Cc: cip-dev@lists.cip-project.org; Nobuhiro Iwamatsu > <nobuhiro1.iwamatsu@toshiba.co.jp>; Pavel Machek <pavel@denx.de>; Biju Das > <biju.das.jz@bp.renesas.com> > Subject: Re: [PATCH 5.10.y-cip 26/29] thermal/drivers: Add TSU driver for > RZ/G2L > > Hi! > > > From: Biju Das <biju.das.jz@bp.renesas.com> > > > > commit 673c68bd48390dad01f7d17670de3e33b60860ac upstream. > > > > The RZ/G2L SoC incorporates a thermal sensor unit (TSU) that measures > > the temperature inside the LSI. > > > > The thermal sensor in this unit measures temperatures in the range > > from > > −40 degree Celsius to 125 degree Celsius with an accuracy of ±3°C. The > > TSU repeats measurement at 20 microseconds intervals and automatically > > updates the results of measurement. > > > > The TSU has no interrupts as well as no external pins. > > > > This patch adds Thermal Sensor Unit(TSU) driver for RZ/G2L SoC. > > > + /* TSU repeats measurement at 20 microseconds intervals and > ... > > + * ts_code_ave = (ts_code[0] + ⋯ + ts_code[7]) / 8 > > + */ > > > + /* The temperature Tj is calculated by the formula > > + * Tj = (dsensor − calib1) * 165/ (calib0 − calib1) − 40 > > + * where calib0 and calib1 are the caliberation values. > > + */ > > I'd avoid using non-ASCII characters where possible. ... is not that much > longer, and that symbol should really be -. > > Also comments should start with /* on separate line, but that's really > detail. > Agreed. Cheers, Prabhakar > Best regards, > Pavel > -- > DENX Software Engineering GmbH, Managing Director: Wolfgang Denk > HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Hi All, This patch series adds support for following to Renesas RZ/RGL SoC: * RSPI * WDT * OSTM * TSU/OPP/IPA All the patches have been cherry-picked from v5.17 release. Cheers, Prabhakar Andy Shevchenko (1): units: Add SI metric prefix definitions Biju Das (22): clk: renesas: r9a07g044: Add WDT clock and reset entries clk: renesas: r9a07g044: Rename CLK_PLL2_DIV16 and CLK_PLL2_DIV20 macros dt-bindings: watchdog: renesas,wdt: Add support for RZ/G2L watchdog: Add Watchdog Timer driver for RZ/G2L clk: renesas: r9a07g044: Add OSTM clock and reset entries dt-bindings: timer: renesas: ostm: Document Renesas RZ/G2L OSTM reset: Add of_reset_control_get_optional_exclusive() clocksource/drivers/renesas-ostm: Add RZ/G2L OSTM support clocksource/drivers/renesas,ostm: Make RENESAS_OSTM symbol visible arm64: dts: renesas: r9a07g044: Add OSTM nodes arm64: dts: renesas: rzg2l-smarc-som: Enable OSTM arm64: dts: renesas: r9a07g044: Add WDT nodes arm64: dts: renesas: rzg2l-smarc-som: Enable watchdog clk: renesas: r9a07g044: Change core clock "I" from DEF_FIXED->DEF_DIV clk: renesas: r9a07g044: Add TSU clock and reset entry clk: renesas: r9a07g044: Rename CLK_PLL3_DIV4 macro clk: renesas: rzg2l: Add CPG_PL1_DDIV macro dt-bindings: thermal: Document Renesas RZ/G2L TSU thermal/drivers: Add TSU driver for RZ/G2L arm64: dts: renesas: r9a07g044: Add OPP table arm64: dts: renesas: r9a07g044: Add TSU node arm64: dts: renesas: r9a07g044: Create thermal zone to support IPA Lad Prabhakar (6): clk: renesas: r9a07g044: Add RSPI clock and reset entries spi: dt-bindings: renesas,rspi: Document RZ/G2L SoC spi: spi-rspi: Add support to deassert/assert reset line spi: spi-rspi: Drop redeclaring ret variable in qspi_transfer_in() arm64: dts: renesas: r9a07g044: Add RSPI{0,1,2} nodes arm64: dts: renesas: rzg2l-smarc: Enable RSPI1 on carrier board .../devicetree/bindings/spi/renesas,rspi.yaml | 4 +- .../bindings/thermal/rzg2l-thermal.yaml | 76 +++++ .../bindings/timer/renesas,ostm.yaml | 20 +- .../bindings/watchdog/renesas,wdt.yaml | 75 +++-- arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 199 +++++++++++++ .../boot/dts/renesas/rzg2l-smarc-som.dtsi | 23 ++ arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi | 14 + drivers/clk/renesas/r9a07g044-cpg.c | 63 ++++- drivers/clk/renesas/rzg2l-cpg.h | 2 + drivers/clocksource/Kconfig | 3 +- drivers/clocksource/renesas-ostm.c | 39 ++- drivers/spi/spi-rspi.c | 27 +- drivers/thermal/Kconfig | 9 + drivers/thermal/Makefile | 1 + drivers/thermal/rzg2l_thermal.c | 239 ++++++++++++++++ drivers/watchdog/Kconfig | 8 + drivers/watchdog/Makefile | 1 + drivers/watchdog/rzg2l_wdt.c | 263 ++++++++++++++++++ include/linux/reset.h | 20 ++ include/linux/units.h | 16 ++ 20 files changed, 1068 insertions(+), 34 deletions(-) create mode 100644 Documentation/devicetree/bindings/thermal/rzg2l-thermal.yaml create mode 100644 drivers/thermal/rzg2l_thermal.c create mode 100644 drivers/watchdog/rzg2l_wdt.c base-commit: 05648080e85d797e727b8935406c2057c8a76637