| Message ID | 20220322030152.19018-3-ctcchien@nuvoton.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | EDAC: nuvoton: Add nuvoton NPCM memory controller driver | expand |
On Tue, 22 Mar 2022 11:01:51 +0800, Medad CChien wrote: > Added device tree binding documentation for Nuvoton BMC > NPCM memory controller. > > Signed-off-by: Medad CChien <ctcchien@nuvoton.com> > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> > --- > .../edac/nuvoton,npcm-memory-controller.yaml | 62 +++++++++++++++++++ > 1 file changed, 62 insertions(+) > create mode 100644 Documentation/devicetree/bindings/edac/nuvoton,npcm-memory-controller.yaml > Acked-by: Rob Herring <robh@kernel.org>
On Tue, Mar 22, 2022 at 11:01:51AM +0800, Medad CChien wrote: > +examples: > + - | > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + ahb { > + #address-cells = <2>; > + #size-cells = <2>; > + mc: memory-controller@f0824000 { > + compatible = "nuvoton,npcm750-memory-controller"; > + reg = <0x0 0xf0824000 0x0 0x1000>; > + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; > + }; > + }; > + .git/rebase-apply/patch:73: new blank line at EOF. + warning: 1 line adds whitespace errors.
Dear Medad, Thank you for your patch. Am 22.03.22 um 04:01 schrieb Medad CChien: > Added device tree binding documentation for Nuvoton BMC > NPCM memory controller. Please use present tense, and spell *devicetree* without a space. The line below even fits in 75 characters: Document devicetree bindings for the Nuvoton BMC NPCM memory controller. > Signed-off-by: Medad CChien <ctcchien@nuvoton.com> > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> > --- > .../edac/nuvoton,npcm-memory-controller.yaml | 62 +++++++++++++++++++ > 1 file changed, 62 insertions(+) > create mode 100644 Documentation/devicetree/bindings/edac/nuvoton,npcm-memory-controller.yaml > > diff --git a/Documentation/devicetree/bindings/edac/nuvoton,npcm-memory-controller.yaml b/Documentation/devicetree/bindings/edac/nuvoton,npcm-memory-controller.yaml > new file mode 100644 > index 000000000000..97469294f4ba > --- /dev/null > +++ b/Documentation/devicetree/bindings/edac/nuvoton,npcm-memory-controller.yaml > @@ -0,0 +1,62 @@ > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/edac/nuvoton,npcm-memory-controller.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Nuvoton NPCM Memory Controller > + > +maintainers: > + - Medad CChien <ctcchien@nuvoton.com> > + > +description: | > + The Nuvoton BMC SoC supports DDR4 memory with and without ECC (error > + correction check). > + > + The memory controller supports single bit error correction, double bit > + error detection (in-line ECC in which a section (1/8th) of the > + memory device used to store data is used for ECC storage). *memory* fits on the line above? > + > + Note, the bootloader must configure ECC mode for the memory controller. > + > +properties: > + compatible: > + enum: > + - nuvoton,npcm845-memory-controller > + - nuvoton,npcm750-memory-controller Sort the entries? Kind regards, Paul > + > + reg: > + maxItems: 1 > + > + interrupts: > + minItems: 1 > + items: > + - description: uncorrectable error interrupt > + - description: correctable error interrupt > + > + interrupt-names: > + minItems: 1 > + items: > + - const: ue > + - const: ce > + > +required: > + - compatible > + - reg > + - interrupts > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + ahb { > + #address-cells = <2>; > + #size-cells = <2>; > + mc: memory-controller@f0824000 { > + compatible = "nuvoton,npcm750-memory-controller"; > + reg = <0x0 0xf0824000 0x0 0x1000>; > + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; > + }; > + }; > +
Dear Borislav, thanks for your comment I will revise it B.R. Medad Borislav Petkov <bp@alien8.de> 於 2022年4月9日 週六 上午1:05寫道： > > On Tue, Mar 22, 2022 at 11:01:51AM +0800, Medad CChien wrote: > > +examples: > > + - | > > + #include <dt-bindings/interrupt-controller/arm-gic.h> > > + ahb { > > + #address-cells = <2>; > > + #size-cells = <2>; > > + mc: memory-controller@f0824000 { > > + compatible = "nuvoton,npcm750-memory-controller"; > > + reg = <0x0 0xf0824000 0x0 0x1000>; > > + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; > > + }; > > + }; > > + > > .git/rebase-apply/patch:73: new blank line at EOF. > + > warning: 1 line adds whitespace errors. > > > -- > Regards/Gruss, > Boris. > > https://people.kernel.org/tglx/notes-about-netiquette
Dear Paul, thanks for your comments Paul Menzel <pmenzel@molgen.mpg.de> 於 2022年4月9日 週六 下午2:12寫道： > > Dear Medad, > > > Thank you for your patch. > > Am 22.03.22 um 04:01 schrieb Medad CChien: > > Added device tree binding documentation for Nuvoton BMC > > NPCM memory controller. > > Please use present tense, and spell *devicetree* without a space. The > line below even fits in 75 characters: > > Document devicetree bindings for the Nuvoton BMC NPCM memory controller. OK > > > Signed-off-by: Medad CChien <ctcchien@nuvoton.com> > > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> > > --- > > .../edac/nuvoton,npcm-memory-controller.yaml | 62 +++++++++++++++++++ > > 1 file changed, 62 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/edac/nuvoton,npcm-memory-controller.yaml > > > > diff --git a/Documentation/devicetree/bindings/edac/nuvoton,npcm-memory-controller.yaml b/Documentation/devicetree/bindings/edac/nuvoton,npcm-memory-controller.yaml > > new file mode 100644 > > index 000000000000..97469294f4ba > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/edac/nuvoton,npcm-memory-controller.yaml > > @@ -0,0 +1,62 @@ > > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/edac/nuvoton,npcm-memory-controller.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Nuvoton NPCM Memory Controller > > + > > +maintainers: > > + - Medad CChien <ctcchien@nuvoton.com> > > + > > +description: | > > + The Nuvoton BMC SoC supports DDR4 memory with and without ECC (error > > + correction check). > > + > > + The memory controller supports single bit error correction, double bit > > + error detection (in-line ECC in which a section (1/8th) of the > > + memory device used to store data is used for ECC storage). > > *memory* fits on the line above? do you mean I should change the term "memory" to others? > > > + > > + Note, the bootloader must configure ECC mode for the memory controller. > > + > > +properties: > > + compatible: > > + enum: > > + - nuvoton,npcm845-memory-controller > > + - nuvoton,npcm750-memory-controller > > Sort the entries? OK > > > Kind regards, > > Paul > > > > + > > + reg: > > + maxItems: 1 > > + > > + interrupts: > > + minItems: 1 > > + items: > > + - description: uncorrectable error interrupt > > + - description: correctable error interrupt > > + > > + interrupt-names: > > + minItems: 1 > > + items: > > + - const: ue > > + - const: ce > > + > > +required: > > + - compatible > > + - reg > > + - interrupts > > + > > +additionalProperties: false > > + > > +examples: > > + - | > > + #include <dt-bindings/interrupt-controller/arm-gic.h> > > + ahb { > > + #address-cells = <2>; > > + #size-cells = <2>; > > + mc: memory-controller@f0824000 { > > + compatible = "nuvoton,npcm750-memory-controller"; > > + reg = <0x0 0xf0824000 0x0 0x1000>; > > + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; > > + }; > > + }; > > +
On Mon, Apr 11, 2022 at 03:57:48PM +0800, Medad Young wrote: > Dear Borislav, > > thanks for your comment > I will revise it Thanks. For the future, please avoid top-posting but put your reply underneath the text you're replying to, like everyone else. Thx.
diff --git a/Documentation/devicetree/bindings/edac/nuvoton,npcm-memory-controller.yaml b/Documentation/devicetree/bindings/edac/nuvoton,npcm-memory-controller.yaml new file mode 100644 index 000000000000..97469294f4ba --- /dev/null +++ b/Documentation/devicetree/bindings/edac/nuvoton,npcm-memory-controller.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/edac/nuvoton,npcm-memory-controller.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Nuvoton NPCM Memory Controller + +maintainers: + - Medad CChien <ctcchien@nuvoton.com> + +description: | + The Nuvoton BMC SoC supports DDR4 memory with and without ECC (error + correction check). + + The memory controller supports single bit error correction, double bit + error detection (in-line ECC in which a section (1/8th) of the + memory device used to store data is used for ECC storage). + + Note, the bootloader must configure ECC mode for the memory controller. + +properties: + compatible: + enum: + - nuvoton,npcm845-memory-controller + - nuvoton,npcm750-memory-controller + + reg: + maxItems: 1 + + interrupts: + minItems: 1 + items: + - description: uncorrectable error interrupt + - description: correctable error interrupt + + interrupt-names: + minItems: 1 + items: + - const: ue + - const: ce + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + ahb { + #address-cells = <2>; + #size-cells = <2>; + mc: memory-controller@f0824000 { + compatible = "nuvoton,npcm750-memory-controller"; + reg = <0x0 0xf0824000 0x0 0x1000>; + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; + }; + }; +